TOPIC : Controllability and Observability UNIT 4 : Design for testability Module 4.1 : Basics of Design for testability TOPIC : Controllability and Observability

Need for Design for testability? IC is tested from the I/O pins. As number of pins increases, the number test vector applied to test the IC exhaustively increases exponentially. Thus, there is a need to modify the circuits by adding a few additional components and pads which reduce the number of I/P pins. This modification of the functional circuit which enables testing simpler and easier is known as Design for testability

Def : Controllability and Observability The ability to induce any signal on a line is known as controllability and, The ability to observe the changes on lines at output is known as observability. These measures controllability is connected with economics (cost of) activating the signal on a given line and, The observability is the cost of propagating the effect of the signal to output pins.

Controllability and Observability The basic concepts used in system for controllability and Observability are : These programs compute a set of values for each line in a circuit. These values are intended to represent the relative degree of difficulty for computing an input vector or sequence for each of the following problems: setting line x to a 1 ( 1 -controllability); setting line x to a 0 ( 0 -controllability); driving an error from line x to a primary output (observability).

Method for increasing controllability and observability Providing a few additional I/P and output points connecting to nodes inside the IC. Many times this calls for provision to isolate different block of the circuit for each other. Provision to inject signal(vectors) through having additional signal generators.

Method for increasing controllability and observability Providing additional registers which may be used for observation of the output of circuit. By providing test engineer and self test facilities extend this to BIST etc.

Poor controllability In general, a circuit node usually has poor random controllability if it requires a unique input pattern to establish the state of that node. A node usually has poor controllability if a lengthy sequence of inputs is required to establish its state. Circuits typically difficult to control are decoders, circuits with feedback, oscillators, and clock generators.

Poor observability A circuit often has poor random observability if it requires a unique input pattern or a lengthy complex sequence of input patterns to propagate the state of one or more nodes to the outputs of the circuit. Less observable circuits include sequential circuits; circuits with global feedback; embedded RAMS, ROMs, or PLAs; concurrent error-checking circuits; and circuits with redundant nodes.

Circuits which are more difficult to access and control Sequential logic is much more difficult to test than combinational logic. Control logic is more difficult to test than data-path logic. Random logic is more difficult to test than structured, bus-oriented designs. Asynchronous designs or those with unconstrained timing signals are much more difficult to control than synchronous designs.

Trade-Off Most DFT techniques deal with either the resynthesis of an existing design or the addition of extra hardware to the design. Most approaches require circuit modifications and affect such factors as area, I/O pins, and circuit delay. Hence, a critical balance exists between the amount of DFT to use and the gain achieved.