1. CS151 Introduction to Digital Design Chapter 5: Sequential Circuits 5-1 : Sequential Circuit Definition 5-2: Latches 1Created by: Ms.Amany AlSaleh

2. 2 Overview  Part 1 - Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams Equivalent states Moore and Mealy Models  Part 2 - Sequential Circuit Design  Part 3 – State Machine Design Created by: Ms.Amany AlSaleh

3. 3 Logic Design- Review Logic Circuits Sequential Circuits Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs an operation that can be specified by a set of Boolean functions. Employ storage elements in addition to logic gates. Outputs are a function of the inputs and the state of the storage elements. Output depend on present value of input + past input. Created by: Ms.Amany AlSaleh

4. 4 Introduction  We have studied only combinational logic thus far.  Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer.  However, in certain cases we might need to store some info before we proceed with our computation or take action based on a certain state that happened in the past.  Combinational circuits cannot remember what happened in the past (i.e. outputs are a function of current inputs).  Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits. Created by: Ms.Amany AlSaleh

5. 5 5-1 Sequential Circuits Definition  A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinatorial Logic: Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. Combinational Circuit InputsOutputs Storage Elements Next State Present State Created by: Ms.Amany AlSaleh

6. 6 Sequential Circuits Definition (Cont.)  Storage elements are circuits that are capable of storing binary information.  The binary information stored in these elements at any given time define the state of the sequential circuit at that time.  Sequential Logic Output function:Outputs = g (Inputs, Present State) Next state function: Next State = f (Inputs, Present State) Combinational Circuit InputsOutputs Storage Elements Next State Present State Created by: Ms.Amany AlSaleh

7. 7 Types of Sequential Circuits  Depends on the times at which: storage elements observe their inputs, and storage elements change their state  Synchronous Behavior defined from knowledge of its signals at discrete instances of time. Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock). Synchronizations is achieved by a timing device called a clock generator which produces a periodic train of clock pulses.  Asynchronous Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable! Created by: Ms.Amany AlSaleh

8. 8 Clocking of Synchronous Circuits  Changes enabled by clock Created by: Ms.Amany AlSaleh

9. 9 Logic Structures for Storing Information  Assuming that the buffer’s propagation delay is t G, and input appears at time t: Figure (a): stores information for a time of t G. Figure (b): stores the 0 indefinitely. Figure (c): stores the 1 indefinitely. Figure (d): a buffer is implemented by cascading a pair of inverters: X’’ = X.  Storage can be constructed from logic with delay connected in a closed loop.  Is there a way to change the information in figures b, c and d?  Solution: replace inverters with NAND or NOR gates  latches ( Asynchronous storage circuit). Created by: Ms.Amany AlSaleh

10. 10 5-2: Latches  Storage elements Maintain a binary state (0 or 1) indefinitely as long as power is delivered to the circuit. Switch states (0  1 or 1  0) when directed by an input signal.  Latches are considered the most basic storage element.  Latches are asynchronous circuits that are used to build more complex synchronous circuits such as Flip Flops.  Types of latches: SR Latches S`R` Latches D Latches X = X Created by: Ms.Amany AlSaleh

11. 11 Cross-Coupled Inverters State 1 State 2  A stable value can be stored at inverter outputs Created by: Ms.Amany AlSaleh

12. 12 SR (Set-Reset) Latches: Asynchronous Storage Elements  Replace the inverters with NOR Gates  Cross-coupling two NOR gates gives the SR Latch.  If Q = 1, set state  If Q = 0, reset state  Usually S=0 and R=0  S=1 and R=1 generates unpredictable results  S & R both 0 in “resting” state  Have to keep both from 1 at same time Created by: Ms.Amany AlSaleh

13. 13 SR Latch (Cont.)  Time sequence behavior: S (set) R (reset) Q Q Logic Diagram Function Table Created by: Ms.Amany AlSaleh

14. 14 SR Latch Operation Created by: Ms.Amany AlSaleh

15. 15 Latch  Similar – made from NANDs  “Cross-Coupling” two NAND gates gives the SR Latch.  Usually S=1 and R=1  S=0 and R=0 generates unpredictable results  S & R both 1 in “resting” state  Have to keep both from 0 at same time Created by: Ms.Amany AlSaleh

16. 16 SR Latch (Cont.)  Which has the time sequence behavior.  S = 0, R = 0 is forbidden as input pattern.  Because the NAND latch requires a 0 signal to change its state, it is referred to as an SR latch. Q S (set) R (reset) Q 1101Now Q “remembers” 0 0011Both go high 1 1??Unstable! Time Logic Diagram Function Table Created by: Ms.Amany AlSaleh

17. 17 Add Control Input: SR Latch  An additional input determines when the state of the latch can be changed!  Is there latch w/ no illegal state? Created by: Ms.Amany AlSaleh

18. 18 Clocked SR Latch  Adding two NAND gates to the basic SR NAND latch gives the clocked SR latch.  The control input C acts as an enable signal for the other two inputs.  The output of the NAND gates stay at logic 1 level as long as C remains at 0.  When control input C goes to 1, information from S and R inputs are allowed to affect the SR latch.  Has a time sequence behavior similar to the basic SR latch except that the S and R inputs are only observed when the line C is high.  C means “control” or “clock”. S R Q C Q 1 1 S` R` Created by: Ms.Amany AlSaleh

19. 19 Clocked SR Latch (Cont.)  The Clocked SR Latch can be described by a table:  The table describes what happens at time (t+1) based on: current inputs (S,R) and current state Q(t). S R Q Q C Created by: Ms.Amany AlSaleh

20. 20 Latch operation enabled by C C Input sampling enabled by gates NOR S-R Latch with Control Input R’ S’ Q’ Q C’ Outputs change when C is low: RESET and SET Otherwise: HOLD Outputs change when C is low: RESET and SET Otherwise: HOLD Latch is level-sensitive, in regards to C Only stores data if C’ = 0 Created by: Ms.Amany AlSaleh

21. 21 D Latch  No illegal state  One way to eliminate the undefined state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time.  Adding an inverter to the SR Latch does that and gives the D Latch with no “indeterminate” states! Created by: Ms.Amany AlSaleh

22. 22 D Latch  State Table of the D latch. Q D Q(t+1) Comment 0 0 0 No change 0 1 1 Set Q 1 0 0 Clear Q 1 1 1 No Change C D Q Q D Q C Q The graphic symbol for a D Latch is: Created by: Ms.Amany AlSaleh

23. 23 Symbols for Latches  SR latch is based on NOR gates  S’R’ latch based on NAND gates  D latch can be based on either.  D latch sometimes called transparent latch Created by: Ms.Amany AlSaleh

24. 24 Summary  Latches are based on combinational gates (e.g. NAND, NOR)  Latches store data even after data input has been removed  S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)  With additional gates, an S-R latch can be converted to a D latch (D stands for data)  D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q  Next time: more storage elements! Created by: Ms.Amany AlSaleh