First results from the DRS4 waveform digitizing chip Stefan Ritt Paul Scherrer Institute, Switzerland

3 ps Timing with the DRS series ASICs Stefan Ritt Paul Scherrer Institute, Switzerland

Requirements High Sampling Speed SNR > 12 bit ps Timing Jitter High Temperature Stability Deep Sampling Depth Many Channels Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon A bit of history… MEG Experiment searching for me g down to 10-13 2001 DRS1 2004 DRS2 2006 DRS3 DRS4 3000 Channels with GHz sampling 2008 Oct. 15th, 2008 Picosecond Workshop, Lyon

How to fulfill all these needs? Design Principles How to fulfill all these needs?

Picosecond Workshop, Lyon The Domino Principle 0.2-2 ns Inverter “Domino” ring chain IN Waveform stored Out FADC 33 MHz Clock Shift Register “Time stretcher” GHz  MHz Keep Domino wave running in a circular fashion and stop by trigger  Domino Ring Sampler (DRS) Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Origin of Jitter VDD/GND noise causes timing jitter! VDD R R GND VDD VDD’ t’ Golden Rules: Make R small  Power Planes Design for steep edges VDD/2 t Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Example: Bus drivers R C Sheet resistance M5: 0.036 W/sq., 4000mm x 0.4 mm  360 W Area capacitance M5-M4: 0.037 fF/mm2+0.036fF/mm  0.35 pF Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Bus driver simulation Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Simulation Result 1 100 mV Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Modified Bus Driver Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Simulaiton Result 2 100 mV Oct. 15th, 2008 Picosecond Workshop, Lyon

More elaborate evaluation Timing-Jitter induced by power supply noise A. Strak, H. Tenhunen, http://www.strak.se/Adam_Strak_DCAS_2006.pdf Oct. 15th, 2008 Picosecond Workshop, Lyon

Rules for high precision timing Keep local power supply stable Low resistive power rails (planes) Separate power supply for inverter chain + PLL from rest Add on-chip decoupling capacitors Try to keep number of simultaneously switching gates minimal Design for fast transitions Identify high load lines, driver them with enough power Follow 1x 3x 10x 30x rule Use differential signalling for critical lines Inverter chain Reference clock input Do not use minimal transistors for critical paths  X DRS4  Oct. 15th, 2008 Picosecond Workshop, Lyon

“Residual charge” problem After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses Solution: Clear before write write clear “Ghost pulse” 2% @ 2 GHz Oct. 15th, 2008 Picosecond Workshop, Lyon

ROI readout mode delayed trigger stop normal trigger stop after latency Trigger stop Delay 33 MHz e.g. 100 samples @ 33 MHz  3 us dead time (3.8 ns / sample @ 8 channels) readout shift register Patent pending! Oct. 15th, 2008 Picosecond Workshop, Lyon

Simultaneous Write/Read FPGA Channel 0 readout 1 Channel 0 Channel 0 Channel 1 Channel 1 1 Channel 1 8-fold analog multi-event buffer Channel 2 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Expected crosstalk ~few mV Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Interleaved sampling 6 GSPS * 8 = 48 GSPS G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) delays (167ps/8 = 21ps) Possible with DRS4 if delay is implemented on PCB Oct. 15th, 2008 Picosecond Workshop, Lyon

New generation of FADCs 8 simultaneous flash ADCs on one chip Require differential input DRS4 has been redesigned with differential output Oct. 15th, 2008 Picosecond Workshop, Lyon

Trigger an DAQ on same board Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GHz samples) though same 8-channel FADCs DRS4 global trigger bus trigger FPGA MUX DRS FADC 12 bit 65 MHz analog front end LVDS SRAM “Free” local trigger capability without additional hardware Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Decisions Usage of external ADC Analog Devices has better engineers Get information faster off-chip (1 sample in 30 ns, 12 bits would need 400 MHz clock) Possibility for continuous sampling ( triggering) Use passive input Hard to design 1 GHz buffer in 0.25 mm technology, needed for 1V linear range Lower power consumption Problem: Bond wire Cparasitic limits bandwidth, high input current 0.8 mA Use Gate-All-Around (GAA) transistors Radiation hardness Good W/L vs. chip area  bigger gates  reduced mismatch On-chip PLL for sampling frequency stabilization Flexible channel configuration Oct. 15th, 2008 Picosecond Workshop, Lyon

Have we achieved the requirements? DRS4 Have we achieved the requirements?

Picosecond Workshop, Lyon DRS4 Fabricated in 0.25 mm 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 8+1 ch. each 1024 bins, 4 ch. 2048, …, 1 ch. 8192 Differential inputs/ outputs Sampling speed 500 MHz … 6 GHz On-chip PLL stabilization Readout speed 30 MHz, multiplexed or in parallel Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon DRS4 packaging DRS4 flip-chip DRS4 DRS3 4.2 mm 9 mm 18 mm Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon On-chip PLL Simulation loop filter DRS4 Phase detector up Vspeed down Measurement Reference Clock fclk = fsamp / 2048 PLL jitter « 100 ps (Spartan-3 jitter 150 ps) “Dead Band” free Does not lock on higher harmonics Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Linear Range (DRS3) Excellent linearity from 0.1V … 1.1V @ 33 MHz readout 0.5 mV max. Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) 850 MHz (-3dB) QFP package Measurement final bus width Simulation Oct. 15th, 2008 Picosecond Workshop, Lyon

Signal-to-noise ratio (DRS3!) “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) Offset Correction Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Timing jitter Inverter chain has transistor variations  Dti between samples differ  “Fixed pattern jitter” “Differential temporal nonlinearity” TDi= Dti – Dtnominal “Integral temporal nonlinearity” TIi = SDti – iDtnominal “Random jitter” = variation of Dti between measurements Dt1 Dt2 Dt3 Dt4 Dt5 TD1 TI5 Oct. 15th, 2008 Picosecond Workshop, Lyon

Fixed jitter calibration Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TDi on a statistical basis Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Sine Curve Fit Method i yji : i-th sample of measurement j aj fj aj oj : sine wave parameters bi : phase error  fixed jitter “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine bi using all measurements where sample “i” is near zero crossing Make several iterations j S. Lehner, B. Keil, PSI Oct. 15th, 2008 Picosecond Workshop, Lyon

Fixed Pattern Jitter Results TDi typically ~50 ps RMS @ 5 GHz TIi goes up to ~600 ps Inter-channel variation on same chip is very small since all channels are driven by the same domino wave Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Random Jitter Results Sine curve frequency fitted for each measurement (PLL jitter compensation) Encouraging result for DRS3: 2.7 ps RMS (best channel) 3.9 ps RMS (worst channel) phase error in fitting sine wave Differential measurement t1 – t2 adds a 2, needs to be verified by measurement Measurement of n points on a rising edge of a signal improves by n Measurements for DRS4 currently going on, expected to be slightly better Oct. 15th, 2008 Picosecond Workshop, Lyon

Inter-Chip Synchronization Trigger t1 Reference Clock Chip 2 t2 PLL Jitter? Oct. 15th, 2008 Picosecond Workshop, Lyon

Rules for Synchronization Synchronize chips with a global low jitter reference clock Determine timing of a hit in respect to global clock (beginning of sampling window) PLL timing jitter < desired accuracy  you’re done PLL timing jitter > desired accuracy  use clock channel with sine ~100 ps jitter  few ps accuracy 8 inputs Shift register Domino + PLL Reference Clock Global Sine Wave Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Chip Comparison Oct. 15th, 2008 Picosecond Workshop, Lyon

Experiments using DRS chip MEG 3000 channels DRS2 MAGIC-II 400 channels DRS2 BPM for XFEL@PSI 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned) Oct. 15th, 2008 Picosecond Workshop, Lyon

Availability DRS4 will become available in larger quantities in November 2008 Chip can be obtained from PSI on a “non-profit” basis Delivery “as-is” Reference design (schematics) from PSI Costs ~ 10-15$/channel Costs decrease if we find sell more… VME boards from industry in 2009 32-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz ext. Trigger Input DRS4 USB 2.0 Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Datasheet Oct. 15th, 2008 Picosecond Workshop, Lyon

Conclusions http://midas.psi.ch/drs Fast waveform digitizing is in my opinion the best choice to achieve ps timing Phase noise of a single cell using a 500 MHz sine wave has been measured to be 3-4 ps in the DRS chip More characterization is needed from community (Single pulse response, 48 GHz mode, …) DRS4 has prospects to come quite a step closer to our goal http://midas.psi.ch/drs Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Simple inverter chain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Oct. 15th, 2008 Picosecond Workshop, Lyon

Design of Inverter Chain PMOS > NMOS PMOS < NMOS Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon “Tail Biting” speed enable 1 2 3 4 1 2 3 4 Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Stopping speed enable 1 2 3 4 enable 1 2 3 4 time Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Stop Schematics WE 1 2 WE 3 D Q D Q D Q RES RES RES 1 2 3 Oct. 15th, 2008 Picosecond Workshop, Lyon

Picosecond Workshop, Lyon Complete Domino Cells Domino Cell 1 Domino Cell 2 Domino Cell 3 Vspeed Enable Write D Q D Q D Q RES RES RES Start Sampling Cell 1 Sampling Cell 2 Sampling Cell 3 Oct. 15th, 2008 Picosecond Workshop, Lyon

On-line waveform display PMTs “virtual oscilloscope” template fit click pedestal histo Oct. 15th, 2008 Picosecond Workshop, Lyon

Constant Fraction Discr. Delayed signal Inverted signal Sum Clock 12 bit Latch Latch Latch Latch + Latch Latch S + <0 & MULT 0 Oct. 15th, 2008 Picosecond Workshop, Lyon