Technology Overview or Challenges of Future High Energy Particle Detection Tomasz Hemperek

Overview Introduction Challenges of radiation and timing requirements by example Possible solutions

Introduction CPIX STAR ALICE-LHC ILC STARALICE-LHCILCATLAS-LHCATLAS-HL-LHC Timing [ns] Particle Rate [kHz/mm 2 ] Fluence [n eq /cm 2 ]> > x x10 16 Ion. Dose [Mrad]> >500 ATLAS Monolithic CMOS 25 2x x >500 ? Requirements for inner pixel layers

Example case 20um 3um 18um (epi)

No radiation 10 Ohm cm - no radiation 0V (PW) 1V (NW) Substrate:10 Ohm cm NW: 1V PW: 0V Electron Concentration

radiation effects (neutrons -> traps) radiation no radiation10 14 n eq /cm 2 Substrate:10 Ohm cm NW: 1V PW: 0V Electron Concentration

STAR Experiment Ladders with 10 MAPS sensors (approx. 2×2 cm each) Ultimate Reticle size (2x2 cm²) Pixel pitch 20.7 µm Array size: 928 x 960 Integration time: µs In pixel CDS Sensors thinned to 50 µm High Res Si option Technology: AMS 0.35u

change substrate to 2k Ohm cm NW: 1V PW: 0V Substrate:2k Ohm cm radiation no radiation10 15 n eq /cm 2 Electron Concentration

Substrate resistivity influence 2k Ohm cm 10 Ohm cm NW: 1V PW: 0V

ALICE Experiment Integrations time: <30us Substrate: hi-res epi Technology: TowerJazz 0.18um CIS To be ready by 2018

Potential difference influence Electrostatic potential Electron Velocity PW: 0V Substrate:2k Ohm cm

k Ohm cm and potential difference Electron Concentration (10 15 n eq /cm 2 ) PW: 0V Substrate:2k Ohm cm

Influence of fill factor 20um 17um

Fill Factor influence at n eq /cm 2 NW: 20V PW: 0V Substrate:2k Ohm cm Dose: n eq /cm 2 Electron Velocity fill factor = 15% fill factor = 75%

Summary % of collected charge in first 10ns no radiation n eq /cm n eq /cm n eq /cm 2 substrate resistivity [Ohm cm] Bias [V] Fill Factor [%] k115 2k2015 2k2075 5x10 15 n eq /cm 2

Conclusions Mind the leakage Need to be fast with charge collection Drift in electrical field New type of sensors

Hybrid Pixel Detectors Monolithic Pixels Depleted Monolithic Pixels

Enabling technologies from: Sensor/Implants (<3nm gate) “High” Resistive Wafers Low Temperature Backside Process 8” hi/mid resistivity silicon wafers that will be qualified by the foundry. What is the influence of CMOS processing? (thermal donors …) Radiation hard process with as many wells as possible. High voltage tolerant. Foundry accepts some process/DRC changes! To achieve backside contact after CMOS processing. Laser activation? from: ion-beam-services.com

Technological support

Bulk process options (simple options, n-on-p) Electronics inside charge collection well  Collection node with large fill factor  rad. hard  Large sensor capacitance (DNW/PW junction!)  x-talk, noise & speed (power) penalties  Full CMOS with isolation between NW and DNW Electronics outside charge collection well  Very small sensor capacitance  low power  Potentially less rad. hard (longer drift lengths)  Full CMOS with additional deep-p implant p-substrate Deep n-well P+ p-well Charge signal Electronics (full CMOS) P+ nw p-substrate n+ p-well Charge signal Electronics (full CMOS) n+ nw deep p-well - - larger capacitance makes it more difficult for the readout

Simple device cross-section high signal (full depletion possible) fast (collection by drift) small pixels limited PMOS in active area input capacitnce dominated by deep-nwell to pwell capacitance

Something better

FD-SOI CHANGE +++

PD-SOI

Other And what about: -Oxide charging (TID) > 100 MRad -How to make readout ? Other options?

Possible scenarios for Active Sensors  Depleted Monolithic Active Pixel Sensor –HR- material (charge collection by drift)  Fully depleted MAPS (DMAPS) Diode + full analog processing Digital only FE chip Wafer to wafer bonding Diode + preamp FE chipDiode + Amp + Digital  Hybrid Pixels with “smart” diodes: - HR- or HV-CMOS as a sensor (8”) - Standard FE chip - CCPD (HVCMOS) on FE-I4  CMOS Active Sensor + Digital R/O chip - HR- or HV-CMOS sensor + CSA (+Discriminator) - Dedicated “digital only” FE chip

Conclusion Particle detection in high radiation environments based on commercial CMOS technologies looks possible Progress in technology and openness of industry for niche applications allows new concept to be realized Possible technology developments for other fields?

Thank you

Backup

High Luminosity LHC Environment - Requirements ATLAS Phase II Letter of Intent Occupancy [%] Inner layer 1.Low power 2.Low material 3.Occupancy 4.Resolution 1.Low cost 2.Low power 3.Low material 4.Resolution hybrid pixels (65nm? + sensor?)low cost hybrid pixels or monolithic? outer Inner Outer layer

High Luminosity LHC Environment - Requirements  Radiation levels:  at 5 cm : ~1500 Mrad ( n eq /cm 2 )  at 25cm : ~100 Mrad (10 15 n eq /cm 2 ) * estimates for 10years of operations

different bias possibilities Substrate:2k Ohm cm Dose: nq/cm 2

nq/cm 2

Trapping in irradiated silicon RD50