Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip.

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Presentation transcript:

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip connections.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Power distribution n Must size wires to be able to handle current—requires designing topology of V DD /V SS networks. n Want to keep power network in metal— requires designing planar wiring.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Low-resistance jumper We want to avoid this:

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Interdigitated power and ground lines V DD V SS

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Power tree design n Each branch must be able to supply required current to all of its subsidiary branches: I x =  b  x I b n Trees are interdigitated to supply both sides of power supply.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Planar power/ground routing theorem n Draw a dividing line through each cell such that all V DD terminals are on one side and all V SS terminals on the other. n If floorplan places all cells with V DD on same side, there exists a routing for both V DD and V SS which does not require them to cross. cell V DD V SS

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Planar routing theorem example A B C V DD V SS V DD V SS cut line no cut line no connection

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Power supply noise n Variations in power supply voltage manifest themselves as noise into the logic gates. n Power supply wiring resistance creates voltage variations with current surges. n Voltage drops on power lines depend on dynamic behavior of circuit.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Tackling power supply noise n Must measure current required by each block at varying times. n May need to redesign power/ground network to reduce resistance at high current loads. n Worst case, may have to move some activity to another clock cycle to reduce peak current.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Clock distribution n Goals: –deliver clock to all memory elements with acceptable skew; –deliver clock edges with acceptable sharpness. n Clocking network design is one of the greatest challenges in the design of a large chip.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Clock delay varies with position

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR H-tree 

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Clock distribution tree n Clocks are generally distributed via wiring trees. n Want to use low-resistance interconnect to minimize delay. n Use multiple drivers to distribute driver requirements—use optimal sizing principles to design buffers. n Clock lines can create significant crosstalk.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Clock distribution tree example

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Floorplanning tips n Develop a wiring plan. Think about how layers will be used to distribute important wires. n Sweep small components into larger blocks. A floorplan with a single NAND gate in the middle will be hard to work with. n Design wiring that looks simple. If it looks complicated, it is complicated.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Floorplanning tips, cont’d. n Design planar wiring. Planarity is the essence of simplicity. It isn’t always possible, but do it where feasible (and where it doesn’t introduce unacceptable delay). n Draw separate wiring plans for power and clocking. These are important design tasks which should be tackled early.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Off-chip connections n A package holds the chip. Packages can introduce significant inductance. n Pads on the chip allow the wires on chip to be connected to the package. Pads are library components which require careful electrical design.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Structure of a typical package

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Package structure n Package body is physical/thermal support for chip. n Cavity holds chip. n Leads in package connect to pads, provide substrate connection to chip.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Some packages DIP PGA PLCC

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Pin inductance n Package pins have non-trivial inductance. n Power and ground nets typically require many pins to supply required current through the packaging inductance.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Pin inductance example Power circuit including pin indutance:

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Pin inductance example, cont’d n Voltage across pin inductance: v L = L di L / dt n Current surge into chip causes inductive voltage drop: –L = 0.5 nH; –i L = 1A; –v L = 0.5 V.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR I/O architecture n Pads are placed on top-layer metal to provide a place to bond to the package. n Pads are typically placed around periphery of chip. n Some advanced packaging systems bond directly to package without bonding wire; some allow pads across entire chip surface.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Pad frame architecture

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Pad frame design n Must supply power/ground to each pad as well as chip core. n Positions of pads around frame may be determined by pinout requirements on package. n Want to distribute power/ground pins as evenly as possible to minimize power distribution problems.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Input pads n Main purpose is to provide electrostatic discharge (ESD) protection. n Gate voltage of transistor is very sensitive—can be permanently damaged by high voltage. n Static electricity in room is sufficient to damage CMOS ICs.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Input pad circuits n Resistor is used in series with pad to limit current caused by voltage spike. n May use parasitic bipolar transistors to drain away high voltages: –one for positive pulses; –another for negative pulses. n Must design layout to avoid latch-up.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Output pad circuits n Don’t need ESD protection—transistor gates not connected to pad. n Must be able to drive capacitive load of pad + outside world. n May need voltage level shifting, etc. to be compatible with other logic families.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Output pad circuit, cont’d.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Three-state pad n Combination input/output, controlled by mode input on chip. n Pad includes logic to disconnect output driver when pad is used as input. n Must be protected against ESD.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Three-state pad circuit

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Boundary scan n Boundary scan is a technique for testing chips on boards. Pads on chips are arranged into a scan chain that can be used to observe and control pins of all chips. n Requires some control circuitry on pads along with an on-chip controller and boundary-scan-mode control pins.