12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 1 A low-power delta-sigma modulator using dynamic-source-follower integrators Ryoto Yaguchi, Fumiyuki Adachi, Waho Takao Department of Information and Communication Sciences Sophia University

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 2 Outline Introduction Introduction Background & Motivation Background & Motivation Our Approach Our Approach Proposed Integrator (DSFI) Proposed Integrator (DSFI) Output Sampling Output Sampling Circuit Simulation Circuit Simulation  Modulators  Modulators 1 st -Order  Modulator 1 st -Order  Modulator 2 nd -Order  Modulator 2 nd -Order  Modulator Performance Comparison Performance Comparison Conclusion Conclusion

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 3 Outline Introduction Introduction Background & Motivation Background & Motivation Our Approach Our Approach Proposed Integrator (DSFI) Proposed Integrator (DSFI) OutputSampling Output Sampling Circuit Simulation Circuit Simulation   Modulators 1 st -Order  1 st -Order  Modulator 2 nd -Order  2 nd -Order  Modulator Performance Comparison Conclusion Conclusion

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 4 Background & Motivation SAR ADC Low power operation Limited resolution  ADC High resolution Higher power  ADC (Opamp) SAR ADC (Opamp-less) Future communication applications need low power and high resolution ADCs. Resolution 1/Power

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 5 Approach Opamp-less Integrator  Modulator Low Power  Modulator Analog INDigital Out We proposed a Dynamic Source Follower Integrator

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 6 Outline Introduction Introduction Background & Motivation Background & Motivation Our Approach Our Approach Proposed Integrator (DSFI) Proposed Integrator (DSFI) OutputSampling Output Sampling Circuit Simulation Circuit Simulation   Modulators 1 st -Order  1 st -Order  Modulator 2 nd -Order  2 nd -Order  Modulator Performance Comparison Conclusion Conclusion

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 7 Dynamic Source-Follower Amplifier (MDAC) 1 ． Sampling Phase 2 ． Amplification Phase Redistributing charges Sampling V in and V ref J. Hu, et al., JSSC ‘09

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 8 Proposed Integrator Dynamic Source-Follower Amplifier （ MDAC) Dynamic Source-Follower Integrator Previous work Proposed Input Sampling

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 9 Proposed Integrator Dynamic Source-Follower Amplifier （ MDAC) Dynamic Source-Follower Integrator Previous work Proposed Feedback path

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 10 Output Sampling Charge Redistributing Two capacitors for charge redistributing and output sampling, indepandently. C2aC2b Feedback path

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 11 Whole Circuit of DSFI

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 12 Simulation of DSFI Bode Plot Input Frequency = 20kHz Sampling Frequency = 0.5MHz Successful integrator operation Input [V] Output [V] Gain [dB] Phase [deg] Time [  s] Input Frequency[Hz] k1k10k100k k1k10k100k 0

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 13 Outline Introduction Introduction Background & Motivation Background & Motivation Our Approach Our Approach Proposed Integrator (DSFI) Proposed Integrator (DSFI) OutputSampling Output Sampling Circuit Simulation Circuit Simulation   Modulators 1 st -Order  1 st -Order  Modulator 2 nd -Order  2 nd -Order  Modulator Performance Comparison Conclusion Conclusion

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 14 1st-Order  Modulator V dacn V dacp Input [V] Output [V] Time [  s] V inp V inn V dacn V dacp V outp V outn V inn V inp V outp V outn V DD

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 15 1st-Order  Modulator Spectrum 1st-order noise shaping characteristics are obtained!! PSD[dB] Frequency [Hz] 20dB/dec 1k 10k100k 1M 10M

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 16 Comparator decision 2nd-Order  Modulator Charging capacitors before comparator decision To 1 st DFSI V outp To 1 st DFSI V outn Redistribution Charging V inp V inn Time 1 st DSFI 2 nd DSFI

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 17 2nd-Order  Modulator Spectrum PSD[dB] Frequency [Hz] 2nd-order noise shaping characteristics are obtained!! 40dB/dec 1k 10k100k 1M 10M

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 18 Performance Comparison Proposed  m, 2 nd -order  modulator has a good power efficiency comparable with those obtained by using  m technologies

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 19 Conclusion We proposed a dynamic source-follower integrator (DSFI), and applied it to opamp-less  modulators. Operation of proposed 1st and 2nd order  modulators designed by using a  m CMOS technology successfully was confirmed by transistor-level circuit simulation. The designed 20-kHz BW, 73.8dB SNR, 2nd-order  modulator has a good power efficiency comparable with those obtained by using  m technologies.

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 20

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 21

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 22 Output Common-mode Voltage Output Common-mode Voltage VCM[V]ENOB [bit] Calculating / Matlab Pass Transistor Ideal Switch

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 23 CMRR at DSFI ・ Output equation of typical differential amplifier : ・ CMRR ： Input p [V] Output [V] Input n [V] Input p [V] Output [V] Input n [V] Time [s] V + +V - =0 V + -V - =0 CMRR is very good!!

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory Clock Generators Non-overlap clock generatorTFF-clock generator Output Time Time Output Input Input Generate φ 1,φ 2 Generate φ 2a,φ 2b Q: Q: For example, what about any digital circuits you needed to control switches?

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory  modulator power consumption 2 nd DSFI 47.1% 1 st DSFI 41.6% Comparator 3.7% Clock Generators 7.1% Others 0.5% Q: Q: In your power consumption estimation, what kinds of circuits are included? *)Without the referential voltage generators

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory Comparison Fairness We have to examine the comparison on experimental measurement, hereafter!! Q: Q: You compared your simulation results with the experimental results. Is this a fair comparison? 2 nd -order DSM 2nd-DSFI 1st-DSFI Clock Generator Comparator 2.5mm