1. ©Alex Doboli 2006  Analog to Digital Converters Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook Email: adoboli@ece.sunysb.edu

2. ©Alex Doboli 2006  ADC The chapter introduces the following aspects: Basic concepts of  ADC & 1sr and 2 nd order ADCs ADC are main subsystems in any embedded system  ADC offer high resolution through two mechanisms: –Oversampling: reduces in-band quantization noise –Noiseshaping: eliminates in-band quantization noise PSoC implementation of  ADC: modulator, decimator, API

3. ©Alex Doboli 2006 Nyquist ADCs Embedded system front end:

4. ©Alex Doboli 2006 Sampling Collect sufficient data for correctly representing a continuous-time signal

5. ©Alex Doboli 2006 Nyquist Sampling Theorem A bandlimited signal can be exactly reconstructed if the sampling Frequency is greater than twice the signal bandwidth Nyquist frequency is twice the signal bandwidth

6. ©Alex Doboli 2006 Sampling aliasing X s (f) = X(f) + X(f+/-f s ) + X(f+/-2f s ) + X(f+/-3f s ) + X(f+/-4f s ) + …

7. ©Alex Doboli 2006 Quantization Quantization is the process of converting the sampled continuous- Valued signals into discrete-valued data

8. ©Alex Doboli 2006 Quantization Discretization range:  = 2 / (2 B - 1) Quantization error: e r ε (-  /2,  /2) White noise x d = x s + e r

9. ©Alex Doboli 2006 Quantization Error Bennett’s conditions: Input does not overload quantizer B is large  is small Joint probability density function of the input at various sampling moments is smooth Quantization error is white noise & is uncorrelated to the input

10. ©Alex Doboli 2006 Quantization Error Quantization noise power Power spectral density  2 e =  2 / 12

11. ©Alex Doboli 2006  Analog to Digital Converter

12. ©Alex Doboli 2006 Oversampling Oversampling frequency Oversampling Ratio (OSR) Advantages of high OSR: simplifies elimination of the images reduced in-band noise power P in-band =  2 e / OSR

13. ©Alex Doboli 2006 Noiseshaping Y(z) = H(z) / (1 + H(z)) X(z) + 1 / (1 + H(z)) E(z) STF NTF

14. ©Alex Doboli 2006  ADC Performance Signal-to-noise ratio (SNR): SNR (dB) = 10 log (signal power) / (in band quantization noise power) –For sinusoidal input: SNR (dB) = 6.02 B + 1.76 (dB) SNR (dB) = 6.02 B + 10 log OSR Dynamic range (DR): –Ratio between the output power for a sinusoidal input with full- range amplitude and the output power of the smallest input signal that it can distinguish and quantize DR (dB) = 10 log (  2 / 8) / (in band quantization noise power) B (bits) = (DR (dB) – 1.76) / 6.02

15. ©Alex Doboli 2006 First-order  Modulator y d (t) = z -1 x(t) + (1 – z -1 ) e(t) STF = z -1 NTF = 1 – z -1

16. ©Alex Doboli 2006 First-order  Modulator: STF & NTF STF NTF High pass

17. ©Alex Doboli 2006 Power Spectrum Density Frequency of the input signal noise shaping

18. ©Alex Doboli 2006  Modulator Performance Signal to noise ratio for sinusoidal input: In-band quantization noise power: P in-band =  2 / (9 OSR 3 ) SNR = 10 log (9 A 2 OSR 3 ) / (2  2 )

19. ©Alex Doboli 2006 Dynamic Range 34 dB (5 bits)

20. ©Alex Doboli 2006 Dynamic Range vs. OSR DR=34db (OSR=32) DR=38dB (OSR=64) DR=42dB (OSR=128) DR=50dB (OSR=256) (8 bits)

21. ©Alex Doboli 2006 PSoC Implementation V in  (-V ref, V ref ) V ref  {V DD /2, 1.6 V bandgap, V external } OSR = 64 V in = (n – 128) / 128 V ref

22. ©Alex Doboli 2006 PSoC Implementation  modulator –Uses programmable SC blocks Decimator –Low pass filtering (eliminates high frequency images) –Downconversion by factor OSR –Sinc 2 filter –Implementation: hardware (integration) – software (differentiation) –Downconversion: timer produces an interrupt after OSR clock cycles & ISR implements differentiations API routines Clocks

23. ©Alex Doboli 2006 Modulator Implementation Single clock for entire design (4 x OSR)

24. ©Alex Doboli 2006 Measured PSD (OSR = 32)

25. ©Alex Doboli 2006 Measured PSD (OSR = 64)

26. ©Alex Doboli 2006 Sinc 2 Decimator Filter (OSR=64) H(z) = [1 / OSR x (1 – z -OSR ) / (1 – z -1 ) ] 2 f b /2 + m f s /2

27. ©Alex Doboli 2006 Sinc 2 Decimator Filter Integration: in hardware using Type 1 decimator block Differentiation: in software at downconversion rate (4 x OSR) Interrupts at 4 x OSR / f s

28. ©Alex Doboli 2006 Timer ISR

29. ©Alex Doboli 2006 API Routines

30. ©Alex Doboli 2006 API Routines

31. ©Alex Doboli 2006 Example

32. ©Alex Doboli 2006 Modeling of jitter noise

33. ©Alex Doboli 2006 Switch Thermal Noise

34. ©Alex Doboli 2006 Switch Thermal Noise

35. ©Alex Doboli 2006 Switch Thermal Noise

36. ©Alex Doboli 2006 OpAmp Noise

37. ©Alex Doboli 2006 Modeling of Slew Rate & Saturation

38. ©Alex Doboli 2006 Second Order  Modulator

39. ©Alex Doboli 2006 Second-order  Modulator

40. ©Alex Doboli 2006 PSoC Implementation