1 The PHENIX Muon Identifier Front End Electronics Andrew Glenn (University of Tennessee), for the PHENIX collaboration Andrew Glenn 5/1/01 April APS Meeting in Washington, D.C.

2 Andrew Glenn 5/1/01 South North The Experiment

3 The Muon Identifier MuID MuTr Andrew Glenn 5/1/ Tubes per arm 3170 Active Channels

4 The MuID Main Functions Distinguish muons from other particles, primarily pions   separation of ~3*10 -3 Provide triggering capability  Large groupings of ORed tubes from lemo pseudo-trigger outputs for commissioning, cosmic-ray trigger, and possible fallback.  Optical fiber outputs for full tracking trigger. (J. Newby V10.008) Andrew Glenn 5/1/01

5 The Muid FEE Main Components In-panel Amplifier/HV Distribution Boards Readout Cards (ROCs) Front End Module Cards (FEMs) Transition Cards, Backplanes, Crates Andrew Glenn 5/1/01 In-panel Amplifiers Transition Cards (20) ROCs (20) FEM (1) LVL1 trigger Twisted-pair cables Optical Fiber Analog signals Optical Fiber Digital Backplane Data Acquisition System Digital Signals (Hits) Basic Data Flow For 1 Orientation

6 In-panel Amplifier/HV Boards Produce Differential Output of ~± 250mV Push Analog Signals Over ~30 meter Twisted-pair Cable Must Stand the Test of Time –Polyfuses –Double-diode protection against broken wire –Diode clamps prevent reverse-bias Andrew Glenn 5/1/01

7 MuID FEE Diagram 16 Six sets of 16 twisted-pair inputs from MuID panels Signal Conditioning -Digitization -Variable Delay Buffering -LVL1 Latency -“Alive for 5” 96 bits out to LVL1 Digital Backplane Data, serial data, control and power Data Formatting Serial Control Timing & Control, eg. Mode bits, LVL1, BCLK G-link to DCM ARCNet in G-link from GTM Andrew Glenn 5/1/01 ROC FEM (20 per Crate) Transition Card 96 Channels

8 MuID ROC Diagram Delay & Latch FPGAs (6) And Clock delay chips (12) Data Store FIFOs (3) Five Event FIFO FPGA Serial String & Pulser Analog Muxes (7) Address Decode PLD Trigger Format FPGA TTL Glink Circuit BCLK Pulser lines Data LVL1_Acpt /RD /RD_EN /DV Analog Spy Output Digital Spy Output Trigger GLink (60 MHz) FIFO cntrl Align bit Trigger Data 6X BCLK Greset ED Locked /RD_EN FPGA Prog. Analog data Analog data P1 P2 /HALT Align bit LVL1_Acpt BCLK Board Resets (4) /RD /DV Data (16) Mode CLK Xfer Mode (2) MP_dat (2) /ALE FEM Device Addr (5) ARCNet Addr/Data (5) Geographic Addr (6) P3 sdin, rdbak, slatch, sclk, sdout, sreset Andrew Glenn 5/1/01 Receiver & Threshold

9 MuID FEM Diagram Mode Control ARCNet Subsystem FIFO GLink XMIT Data Formatter Diagnostic FPGA Address Decode PLD Glink RCV Strobe, /CAV, /DAV Data (16) WR Clk & EN (2) Mode Bits (20) Serial Data (6) ARC bus (10) FPGA Program (6) 6 Command Lines (7) Glink To DCM ARCNet Serial line RD Clk & EN (2) Data (16) FPGA Program (6) LVL1 accept BCLK 4xBCLK EnDat0 User Bit [2:0] Mode Bits [7:0] Mode Enable ROC Data FEM Addr /ALE /RD /ROC_DV /HALT LVL1 Acpt BCLK Resets (4) Align bit FPGA Geographic Address (6) ARC Addr/Data Mode CLK Xfer Mode (2) MP_dat (2) Rx Reset Stat0 Address & RD Cntrl (7) Glink From T&C Andrew Glenn 5/1/01 Data Formatter

10 Other Components Andrew Glenn 5/1/01 Transition Card Crate Digital Backplane Passthrough backplane 2 Crates per rack: 1 for horizontal tubes and 1 for vertical

11 MuID FEE Photos FEM Signal Wires FEM Andrew Glenn 5/1/01 Pseudo-trigger outputs To Trigger

12 Communication Overview Slow Controls (Timing Delays, Thresholds …) –Serial Downloads via ARCNet to FEM Timing and Modebits from Granule Timing Module (GTM) –Fiber Optic G-Link (On FEM) Formatted Data to Data Collection Module (DCM) –Fiber Optic G-Link (On FEM) Level1 Trigger –Lemo Cable Pseudo-trigger outputs (commissioning) –6x Fiber Optic G-Link (Full Tracking Trigger) Andrew Glenn 5/1/01

13 ARCNet GUIs Andrew Glenn 5/1/01 Java based GUIs set various parameters over ARCNet via a CORBA server. Three Types of Downloads: -DMUX (Shown) -DAC -Miscellaneous

14 Current FEE Status Successful basic commissioning run last year. (H. Sato V10.006) All FEMs have passed quality assurance tests. All ROCs have passed quality assurance tests. Noise and trigger studies at an advanced stage. Data in ~1 Month! Please see additional information. Andrew Glenn 5/1/01