12/3/2015 Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits Digital Testing: Test Pattern Generation

12/3/2015Copyright©2001, Samiha Mourad2 Outline Types of Tests Deterministic Tests Notations and Basic Operations Design Verification Critical Path D-Algorithm Reconvergent Fanout PODEM Other Algorithms

12/3/2015Copyright©2001, Samiha Mourad3 Deterministic Tests NP-complete problem Algebraic: Boolean Difference General Fault Objective Critical Path Pseudo Random Algorithmic D-Algorithm Roth 1967 IBM PODEM Goel 1981 IBM FAN Fujiwara 1983 Kyoto U. Socrates Schultz 1988 Germany 0/1 propagation Rajski 1990

12/3/2015Copyright©2001, Samiha Mourad4 E=1 G3 G4 G5 G 6 W/1 U = 0 Z V H=1 F G G1 B=0 A=0 Justification Sensitization or Propagation G2 Implication C 0 Justification The Basic Operations W sa1 fault

Critical path tracing if only one input has controlling value => such input is critical if all inputs have value c’ => all inputs are critical A signal is critical if its change causes the gate output change

12/3/2015Copyright©2001, Samiha Mourad6 Critical Path G2 G3 G4 G5 X=0 W=1 U=0 Z=1 Y H=0 F=0 G=1 G1 A B=1 G2 G3 G4 G5 X=1 W=1 U Z=1 Y=1 H=1 F=1 G=0 G1 A=0 B=0 (a) (b) Critical signals

Critical path tracing critical signals C OutIn OutIn AND start with the OR output and NAND propagate path NOR towards input single all

Critical path tracing Example: Start with critical 0 c at the output and propagate the critical signals backwards abab c g dede hijkhijk l f

Critical path tracing Example : Make it critical by setting c to 1 Faults detected by the input (abde) = 0000 => a1, b1, d1, e1, h0, i0, j0, k0, l0 a b c d e f g h i j k l 0 C 1 C 1 C 1 C 1 C 0 C 1 0 C 1 0 C 0 C 1 abab c g dede hijkhijk l f

Critical path tracing Example: Find critical paths for q = 0 c abcdefghiabcdefghi jklmnjklmn opop q

Critical path tracing Example : a b c d e f g h i j k l m n o p q 0 C 0 C 0 C 0 C 1 C 0 C 1 1 C 1 C 1 C 1 C C 0 C 0 1 C abcdefghiabcdefghi jklmnjklmn opop q

Fault Oriented Algorithms

12/3/2015Copyright©2001, Samiha Mourad14 A Generic Test Algorithm Fault Oriented Algorithms

Function of NAND Gate c Input a 01XD XD X1XXXX D1X1 1DX1D D D D D D a b c D 1/0 0/1 D 1 Input b

D-Algorithm Use D-algebra Activate fault Place a D or D at fault site Do justification, forward implication and consistency check for all signals Repeatedly propagate D-chain toward POs through a gate Do justification, forward implication and consistency check for all signals Backtrack if A conflict occurs, or D-frontier becomes a null set Stop when D or D at a PO, i.e., test found, or If search exhausted without a test, then no test possible

Definitions Justification: Changing inputs of a gate if the present input values do not justify the output value. Forward implication: Determination of the gate output value, denoted as X, according to the input values. Consistency check: Verifying that the gate output is justifiable from the values of inputs, which may have changed since the output was determined. D-frontier: Set of gates whose inputs have a D or D, and the output is X.

Line justification in a fanout-free circuit Justify (l, val) begin set l to val if l is a PI then return /* l is a gate (output) */ c = controlling value of l i = inversion of l input_val = val  i if (input_val = c’) then for every input j of l Justify (j, input_val) --recursive call else begin select one input (j) of l Justify (j, input_val) end l0 l x0xx0x 1 l j j

Error propagation in a fanout-free circuit Propagate (l, err) /* err is D or D’ */ begin set l to err if l is PO then return k = the fanout of l c = controlling value of k i = inversion of k for every input j of k other than l Justify (j, c’) Propagate (k, err  i) end 1 err 1 err’ k l=

Definition: Singular Cover A singular cover defines the least restrictive inputs for a deterministic output value. Used for: Line justification: determine gate inputs for specified output. Forward implication: determine gate output. a b c XXXX 0 Examples:XX0 ∩ 110 = 110 0XX ∩ 0X1 = 0X1

Definition: D-Cubes D-cubes are singular covers with five-valued signals Used for D-drive (propagation of D through gates) and forward implication. a b c XDXD X Examples:XDX ∩ 1DD = 1DD 0DX ∩ 0D1 = 0D1 DDX ∩ DD1 = DD1

12/3/2015Copyright©2001, Samiha Mourad22 Operations PDCF Propagation D-cube Justification X = D (b) (a) D' D {W,X,F} ={ 1,D,D} A = 0 B = 0 W = 1 X = D F = D (c) {W,X,F} ={ 1,D,x} W = 1 F = x X = D W = 1 F = 1 E = x W = x E = x F = 1

set selected inputs to D (D’) set remaining inputs to c’ the output is D  i (D’  i) Example: For OR gate with (c=1, i=0) and input D set the remaining inputs to 0 and the output is D Propagation D-cubes

all inputs to c’ (c) if i = c one input to c (c’) if i’ = c (other don’t care) Example: for AND gate (c=0, i=0) and output equal to D (1/0) use all inputs equal to 1 Primitive D-cubes of fault for output equal to D (D’) set :

D-Intersection ∩01XD X01XD DDD D D D D Undefined State (conflict) D

12/3/2015Copyright©2001, Samiha Mourad26 Intersection Operation  01xDD’ 0 0  0  1  11  x 0 1x DD’ D  D D  D'  D’  D'  is the nul set, there is no intersection  the value depends on the context of the operation Rules to intersect D-cubes are the same as for generation of primitive D-cubes of faults

12/3/2015Copyright©2001, Samiha Mourad27 Set Operations

Testing for single stuck faults Error propagation in a fanout-free circuit Example : Propagate error in the following circuit j h i abcdeabcde f sa0 g

Testing for single stuck faults DjDj h i abcdeabcde f sa0 g 110x0110x0 D1D1 D0D0 Error propagation in a fanout-free circuit Example : Propagate error in the following circuit

Testing for single stuck faults Example : Propagate 6 sa0 fault in the circuit G1 G2 G3 G4 sa G5

Testing for single stuck faults Example : Propagate 6 sa0 fault in the circuit G1 G2 G3 G4 sa G5 D 0 D’ 1 D X

Testing for single stuck faults Example : G1 G2 G3 G4 G X 1 0 X 0 D 0 X 10 D D’1 D D’ 1 X 0 0 X D X 0 1D 0 D’ D 1 D’ D’ 1 1 0D D D’D D D’ singular pdcf singularpropagationpropagation cover coverD-cubeD-cube G1 G2 G3 G4 sa G5

Testing for single stuck faults Example : Resulting test for 6 sa0 : T = 10x branch X 0 D Y 0 X 0 D D’ Y 0 X 0 D 1 D’ D Y 0 X 0 0 D 1 D’ D N 1 0 X 0 0 D 1 D’ D N D-drive 1, select pdcf for 6 sa0 2, propagate through G4 3, propagate through G5 Consistency 4, use singular cover of G3 5, use singular cover of G1 G1 G2 G3 G4 sa G5

An Example: XOR a b a2 a1 b1 b2 c1 c c2 d e f Find tests for:c sa0 c1 sa0 c2 sa0

XOR: Test for c sa0 a b a2 a1 b1 b2 c1 c c2 d e f ActionOperationD-frontier 1.Activate faultc=1 or c=c1=c2=Dd, e 2.Justify c=10X1, a=a1=a2=0d, e 3.Forward impl a2=00D1, d=1e 4.Forward imp d=11XX, no implication possiblee 5.D-drive c2→eD1D, b2=b=b1=1, e=Df 6.Forward impl b1=1011, consistency checkedf 7.D-drive e→f1DD, f=DPO 8.Stop, test foundTest: (a,b) = (0, 1), f = 1

Test-Detect: XOR, Test (0,1) Determine good circuit signal values. For each fault Place a D or D at the fault site Perform forward implications Fault is detected if any PO assumes a D or D value a b a2 a1 b1 b2 c1 c c2 d e f b1 b2 D for c1 sa0 D for c2 sa0 D D 0D1 (null D-frontier) → c1 sa0 not detected D1D 1DX ∩ 1DD = 1DD, D at PO → c2 sa0 is detected

XOR: Test for c1 sa0 a b a2 a1 b1 b2 c1 c c2 d e f ActionOperationD-frontier 1.Activate faultc1=1 or c=c2=1, c1=Dd 2.Justify c=10X1, a=a1=a2=0 d 3.Forward impl a2=00D1, d=1null 4.Back-up, redo step 3No choice availablenull 5.Back-up, redo step 2X01, b=b1=b2=0, a=X, d=Xd 6.Forward impl b2=0101, e=1d 7.Forward impl e=1X1X, no implication possibled 8.D-drive c1→d1DD, a2=a=a1=1,d=Df 9.Forward impl a1=1101, consistency checkedf 10.Forward impl d=DD1D, f=DPO 11.Stop, test foundTest: (a,b) = (1, 0), f = 1

An Example The circuit will be used to illustrate the D-algorithm for faults on three different nodes an internal node X a primary input Y a primary output Z

12/3/2015Copyright©2001, Samiha Mourad39 Node X sa0 Fault

12/3/2015Copyright©2001, Samiha Mourad40 Compact Table

12/3/2015Copyright©2001, Samiha Mourad41 Input Y sa1 Fault 1OperationGateABXYWUFGHZ 2Initializationxxxxxxxxxx 3PDCFYxxxD’xxxxxx 4D frontierG4xxxD’xx1x x 5ImplicationF=1xxxD’xx10 x 6D frontierG5xxx D’ xx10 7JustificationF =1xx1D’1 x  0 D' 8JustificationX= D’1x  0 D'

12/3/2015Copyright©2001, Samiha Mourad42 Output Z sa0 Fault

Multiple-Valued Algebras Symbol D 0 1 X G0 G1 F0 F1 Alternative Representation 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Faulty Circuit X 0 1 Fault-free circuit X 0 1 X Roth’s Algebra Muth’s Additions

Complexity of D-Algorithm Signal values on all lines (PIs and internal lines) are manipulated using 5-valued algebra. Worst-case combinations of signals that may be tried is 5 #lines For XOR circuit, 5 12 = 244,140,625. Podem: A reduced-complexity ATPG algorithm Recognizes that internal signals depend on PIs. Only PIs are independent variables and should be manipulated. Because faults are internal, a PI can assume only 3 values (0, 1, X). Worst-case combinations = 3 #PI ; for XOR circuit, 3 2 = 8.

Podem: Path oriented decision making Step 1: Define an objective (fault activation, D-drive, or line justification) Step 2: Backtrace from site of objective to PIs (use testability measure guidance) to determine a value for a PI Step 3: Simulate logic with new PI value If objective not accomplished but is possible, then continue backtrace to another PI (step 2) If objective accomplished and test not found, then define new objective (step 1) If objective becomes impossible, try alternative backtrace (step 2) Use X-PATH-CHECK to test whether D-frontier still there – a path of X’s from a D-frontier to a PO must exist. Podem Algorithm

XOR Example Again (1,1)6 (3,2)5 (4,2)3 (5,5) Compute SCOAP testability measures: (CC0,CC1)CO 7 7

Podem: Objective and Backtrace (1,1)6 (3,2)5 (4,2)3 (5,5) sa0 1. Objective 1: set fault site to 1 0 2&3. Backtrace to a PI and simulate 1 1 D X-path check fails → Back up: Erase effects of steps 2&3 Try alternative backtrace 7 7

Podem: Back up (1,1)6 (3,2)5 (4,2)3 (5,5) sa0 1. Objective 1: set fault site to 1 0 4&5. Alt. backtrace to a PI and simulate 1 1 D X-path check: OK Objective 1 achieved X-path 7 7

Podem: D-Drive (1,1)6 (3,2)5 (4,2)3 (5,5) sa0 4. Objective 2: D-drive, set line to Backtrace to a PI and simulate 1 1 D 1 D D 0 D at PO →Test found 7 7

Another Podem Example 1. Objective “0” 2. Backtrace “A=0” 3. Logic simulation for A=0 (9, 2) S-a Objective possible but not accomplished yet

Podem Example (Cont.) 1. Objective “0”5. Backtrace “B=0”6. Logic simulation for A=0, B=0 7. Objective possible but not accomplished yet (9, 2) S-a

Podem Example (Cont.) 9. Logic simulation for E=0 10. Objective possible but not accomplished yet (9, 2) 0 S-a-1 1. Objective “0” 0 8. Backtrace “E=0”

Podem Example (Cont.) 11. Backtrace “D=0” 12. Logic simulation for D=0 13. Objective accomplished (9, 2) S-a-1 1. Objective “0”

12/3/2015Copyright©2001, Samiha Mourad57 PODEM Flowchart

12/3/2015Copyright©2001, Samiha Mourad58 PODEM Example E sa1 Fault U W X Assign x to all inputs 2.Assigning 0 to the primary input, U, causes E = 1; hence, this choice does not further our goal and it is discarded. Then U =1 3.We proceed with W = 1. The implication of this value is not furthering the objective nor is it blocking it. 4.X = 1 is rejected and X=0 is selected. 5.This Implies F=0, H=0 and we can propagate D’ on G, then D on the primary output, Z. =D’ G2 G3 G1 G4 G5 X W U Z Y H F G E =D

12/3/2015Copyright©2001, Samiha Mourad59 PODEM Example G sa1 Fault 1.Assign x to all inputs 2.Assigning 0 to the primary input, W, causes G = 1; hence, this choice is discarded. Then W =1 which causes F=0. 3.We proceed with X = 1. The implication of this value is not furthering the objective nor is it blocking it. 4.Similarly V=1 is selected. 5.E=1 is rejected, so E=0 which implies I=1 and we can propagate D on the primary output, Z. =D’ =D

12/3/2015Copyright©2001, Samiha Mourad60 Other Algorithms FAN A variation of PODEM with better heuristic to prune the search tree for backtracking Socrates A variation of FAN using testability analysis to cut down on backtracking

12/3/2015Copyright©2001, Samiha Mourad61 Comparing FAN to PODEM Computing TimeAverage Backtracks%age of Faults Aborted CircuitPODEMFANPODEMFANPODEMFAN

Multi fault detection with 01 sequence (Dr. Janusz Rajski) 1, Drive backward from output 01 to establish 2 test vectors 2, Propagate forward (with fault effects) 3, Analyze the results (backward)

Rajski’s method Example : ABCE = (00, 11, 01, 11) G7 01,11,0 0 E=11,00 A=00,11 B’=00,11 C=01,00,11 B=11,00 G2=01,00,11 G3=00,11 G4=10,11,00 G5=01,11,00 G1=01,00,11 G8=00,11 G6=00,10,11 If single fault

Rajski’s method Example : ABCE = (00, 11, 00, 10) G7=01 E=10,11 A=00 B’=00,11 C=00 B=11 G1=00 G2=00 G3=01,00,11 G4=11,00 G6=01,00 G8=01,00,11 G5=00

Rajski’s method Example : ABCE = (10, 00, 00, xx) G7=01 E=xx A=10 B’=11 C=00 B=00,11 G1=00 G2=10 G3=11 G4=01 G5=00,10 G6=01

Rajski’s method Example : multiple faults coverage sa1sa0 Ax3 B3x Cxx E2x G1xx G2xx G3x2 G432 G5xx G6x2 G7xx G8x2

Rajski’s method Example : 01,11,00 abcdefabcdef Z ghgh 00,11 01,11,00 11,00 01,00,11 00,11 01,11,00 00,11 11,00 01,11,0000,11 h1 = 01,11,00 h2 = 01,11,00 i j k Multiple faults sa0sa1 ax bx cxx dx ex fx gx hxx h1x h2x ix jx kxx Zxx

Rajski’s method 01,00,11 abcdefabcdef Z ghgh 10,00,11 11,00 01,00,11 00,11 11,00 01,00,11 11,00 00,11 11,00 01,00,1100,11 h1 = 11,00 h2 = 11,00 i j k if single fault sa0sa1 a2x bx cxx dx ex fx gx2 hxx h1x h2x ix2 jx kxx Zxx Example :

Rajski’s method G7 01,11,0 0 Example : ABCE = (00, 11, 01, 11) single fault test – critical signals are underlined E=11,00 A=00,11 B’=00,11 C=01,00,11 B=11,00 G2=01,00,11 G3=00,11 G4=10,11,00 G5=01,11,00 G1=01,00,11 G8=00,11 G6=00,10,11

Example : Using Rajski’s method

01,00,11 10,00,11 00,11 10,00,11 01,00,11 00,11 11,00 00,11 11, ,11 Example : Using Rajski’s method