DAQ for 4-th DC S.Popescu

Introduction We have to define DAQ chapter of the DOD for the following detectors –Vertex detector –TPC –Calorimeter –Muon system

Vertex detector We will use most probably the CCD readout chips –They have good integration –low noise and capacitance  expected 60 e/pixel We have 5 inner layers of pixels Inner layer: –Assume is 20  * 20  pixels  inner radius 1.5  angular resolution radians –assume 10 Mpixels CCD being available  first inner layer requires 190 Mpixels 19 CCD chips Using a projective geometry we have the followings Second layer scales by factor of 4 with same pixel size  80 chips Third layer  scaling factor 7  140 chips ; Forth layer  scaling factor 10  200 CCD chips Fifth layer – factor is 13  260 CCD chips Total  700 CCD chips

Vertex detector For designing the readout strategy we have the following starting points: –data volume is 10 9 pixels (bits) –CCDs: Kodak KAF-6300 chip: 6Mpix, 9  pix size, chip size = 27.6 * 18 mm 2, 550 nm - Kodak KAF chip: 16 Mpix, 9  pixel size, 36.9 * 36.9 mm2 –Max CCD readout rate ~ 50 Hz ( Motion picture video 48 fps) –Bandwidth = f(Trigger rate). –Repetitive Auto-Trigger by clock downcounting (every 20 ms you can take the next event) –1 Hz =12.5 Mbyte/s … 48 Hz = 600 MBytes/s –20 Hz max fits with 1 Gbit ethernet links –48 Hz max fits with 10 Gbit ethernet links –Transmit zer0-suppressed pixel data as IP packets out of FPGA buffer to Gigabit MAC chip (LHCb) - Event building automatic due to packet routing to same IP address -controller collects next free CPU buffer -controller distributes IP addresses backwards to FPGA

Vertex CCD readout scheme Pix1ZsuppBuff Pix2ZsuppBuff Pix3ZsuppBuff PixnZsuppBuff FPGA Pix1ZsuppBuff Pix2ZsuppBuff Pix3ZsuppBuff PixnZsuppBuff FPGA ROUTERROUTER GBE fiber CPU farm Pix1ZsuppBuff Pix2ZsuppBuff Pix3ZsuppBuff PixnZsuppBuff FPGA GBE fiber Readout clock / trigger MAC GBE fiber Next Event memories GBE fiber or copper Eventbuilding by IP packet routing to event-memories ILC clock Clock distribution Readout trigger/Ev Nr. Make IP packet in FPGA 48 fps

TPC We will use the TPC from EURODET R&D The pad size for our case could be 2x6 mm  channels Technology not yet final we will have to think soon at this

Calorimeter (crystal + fiber) Main technology is the APD or Silicon PM pixels For crystals the baseline solution is the APD Based on recent PWO/APD readout electronics for the Alice PHOS + EMCal (fiber calorimeter), 14 bit dyn range + single ch. APD gain control. Altro –TPC readout backend. With China, plans for upgrade R&D for direct optical GBE readout and 16 bit dyn. range.

PHOS crystal mapping with FEE Double Strip Unit for 2*8 Crystals Left-Right orientation of 2 double Strip Units = 1 FEE card (plugged below) read 2 || row L R FEE card APD PWO

Calorimeter readout 1.) Crystals: 16 bit dyn. range (5MeV-325 GeV linear range per channel ) Large surface APD (5*5 mm2 like CMS) ?Operate at -25 C for 3* increased light yield (PWO) ?? Preamplifier: charge sensitive like Alice with 1V/pC APD readout: dual shapers/ gain ratio= 2**4 -> requires two 12 bit ADCs per channel => 24 bit data per ADC sample Shaping time 200ns – 1us for noise 1000 – 280 electrons Sampling frequency 10 MHz -2 MHz corresp. to above Assume 1us shaping/5 MHz sampling: -> 2 us peaking time ( 2 nd ordev shaper) -> 32 ADC samples + 8 pre-samples * 5 MHz -> 8 us semi-gaussian envelope recording to buffer ->1 kbyte stored data per APD (crystal) Self –triggered 1 kHz -> Bandwidth =1 Mbyte/s per APD Bandwidth ~ 80 Mbyte/s Offline fit with Gamma-2 yields time reference at y’=0 ( +- 1 ns) above 1 GeV 2.) Fibers: Si-PM readout px 1*1 mm2 ( ) No preamplifier. 10 bit dyn range enough -> use only 1 ADC = 12 bit /channel ignore 2 bits Assume 500 ns shaping time/ 10 MHz sampling -> 1 us peaking time -> 64 ADC samples + 8 pre-samples -> 7.2 us semi-gaussian envelope in buffer -> 0.5 kbyte stored data per SiPM (fiber) Self triggered 1 kHz -> Bandwidth = 0.5 Mbyte/s per Si-PM Bandwidth 20 Mbyte/s Timing resolution: order 1 ns

Calorimeter readout ROUTERROUTER GBE fiber CPU farm GBE fiber Readout clock / trigger GBE fiber Next Readout Controller Event memories GBE fiber or copper GBE Eventbuilding by IP packet routing to event-memories ILC clock Distribution of next event memory address via IP to FPGAs Clock distribution FPGA MAC Readout trigger APD Shaper/ADC Buff 24 HV-biasAPD APD Shaper/ADC Buff APD Shaper/ADC Buff FPGA MAC Readout trigger APD Shaper/ADC Buff 24 HV-biasAPD APD Shaper/ADC Buff APD Shaper/ADC Buff FPGA MAC Readout trigger SiPM Shaper/ADC Buff 12 HV-bias SiPM SiPM Shaper/ADC Buff SiPM Shaper/ADC Buff Pre-router Next

Muon system We will use the cluster counting drift chambers To maximasize resolution vs cell size (4cm*4cm) The read-out scheme will be based on fast flash ADC in range of Gsample/s

Conclusions We are in the designing phase of our DAQ This is a first estimation to define our read out strategy Soon will have to think on our software DAQ We are welcoming people if are interested in joining this subject