1. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 1 Vertex Readout Joel Goldstein PPd, RAL 4 th ECFA/DESY LC Workshop DAQ Session 1 st April 2003

2. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 2 Outline 1.Vertex detector conceptual design 2.CP CCD technology option 3.Planned readout scheme 4.Other scenarios (More demanding TESLA environment used throughout)

3. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 3 The Vertex Detector 5 layers (15-60mm) ~ 0.1% X 0 per layer 20  m  20  m pixels 800 million channels Background rates force readout  –50  s for Layer 1 –250  s for Layer 2

4. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 4 Column Parallel CCDs Separate readout for each column Readout chip bump-bonded to CCD Chips contain: –Amplifiers –5-bit FADCs –Filters –Sparsification logic –Local memory

5. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 5 Detector Parameters Layer Radius /mm CCD L  W /mm CCDs /ladder No. of lad’s Clock /MHz RO Time /  s Bkgd kHits /train 115 100  13 1850 761 226 125  22 2825250367 337 125  22 21225250141 448 125  22 2162525028 560 125  22 2202525028

6. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 6 Ladder Readout Layer 1 read out 20 times per bunch train  50k z pixels Layer 2 read out 5 times per bunch train  31k z pixels –31 bits/4 bytes pixel address

7. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 7 DAQ Plan 4.4 billion pixels  5 bits = a lot of data! So, 1.Sparsify locally into clusters (2  2,…) 2.Store on chip 3.Readout during 200ms dead time 1.3 million hits = 20 Mbytes per bunch train

8. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 8 Detector Level DAQ

9. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 9 Front End Readout Chain

10. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 10 Other Scenarios NLC: Bkgd hits/train ~ 0.1  TESLA Readout in 8.3 ms dead time TESLA 800: 2  bunches/train Same CCD clock speed More capacity in readout? –Memory, datalinks etc. –Still to be looked at Active Pixels: Similar schemes feasible

11. Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 11 Summary 800 MPixel CP CCD vertex detector Clustering and sparsification performed on readout chip ~10 Mbytes per bunch train per end Single interface card per end, outside tracking volume Minimal external connections –input control fibre, output data fibre, power Other technologies similar Testing of first CP CCDs and readout chips starting