University of Tehran 1 Microprocessor System Design Memory Timing Omid Fatemi

University of Tehran 2 Outline Reading / Writing memory Timing requirements - microprocessor side Timing of 6264 and 2764 Slow memories and wait states DRAM interfacing RAS / CAS signals DRAM in PC

University of Tehran 3 Writing Sequence of steps –Setup address lines –Setup data lines –Activate write line (maybe a pos edge) –Usually latch on the next edge

University of Tehran 4 Writing

University of Tehran 5 Reading Steps –Setup address lines –Activate read line –Data available after specified amt of time

University of Tehran 6 Reading

University of Tehran 7 Processor Timing Diagram for any memory read machine cycle

University of Tehran 8 Processor Timing Diagram for any memory write machine cycle

University of Tehran 9 Chip Select Usually a line to enable the chip

University of Tehran 10 Minimum Mode

University of Tehran 11 Minimum Mode When Memory is selected?

University of Tehran 12 Minimum Mode 2 20 bytes or 1MB

University of Tehran 13 When interfacing memory chips to a microprocessor, consider the following: TAVDV – address access time TRLDV – read access time TDVWH – memory setup time TWHDX – data hold time TWLWH – write pulse witdth Refer to 8088 data manual8088 data manual

University of Tehran 14 Address Access Time (TAVDV)

University of Tehran 15 Timing Requirements during Memory Read TAVDV –3TCLCL – TCLAV – TDVCL –Address Access Time –from Address is Valid to Data is Valid

University of Tehran 16 Read Access Time (TRLDV)

University of Tehran 17 Timing Requirements during Memory Read TRLDV –2TCLCL – TCLRL – TDVCL –Read Access Time –from Read Signal is Low to Data is Valid

University of Tehran 18 Memory Setup Time (TDVWH)

University of Tehran 19 Timing Requirements during Memory Write TDVWH –2TCLCL – TCLDV +TCVCTX –Memory Setup Time –from Data is Valid to Write Signal is High

University of Tehran 20 Data Hold Time (TWHDX)

University of Tehran 21 Timing Requirements during Memory Write TWHDX –TCLCH – X –Data Hold Time (after WR ’ ) –from Write Signal is High to Data is Invalid (Inactive)

University of Tehran 22 Write Pulse Width / Write- Time (TWLWH)

University of Tehran 23 Timing Requirements during Memory Write TWLWH –2TCLCL – Y –Write Pulse Width / Write-Time –from Write Signal is Low to Write Signal is High

University of Tehran MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

University of Tehran 25 Computation of Timing Requirements for 8088 using a 4Mhz Clock TAVDV  3TCLCL – TCLAV max – TDVCL min  3(250 ns) – 110 ns – 30 ns  610 ns TRLDV  2TCLCL – TCLRL max – TDVCL min  3(250 ns) – 165 ns – 30 ns  555 ns

University of Tehran MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

University of Tehran 27 Computation of Timing Requirements for 8088 using a 4Mhz Clock TDVWH  2TCLCL – TCLDV max +TCVCTX min  2(250 ns) – 110 ns + 10 ns  400 ns TWHDX  TCLCH – X  118 ns – 30 ns  88 ns TWLWH  2TCLCL – Y  2(250 ns) – 60 ns  440 ns

University of Tehran 28 Timing Requirements for 8088 using a 4Mhz Clock TAVDV = 610 ns TRLDV = 555 ns TDVWH = 400 ns TWHDX = 88 ns TWLWH = 440 ns

University of Tehran 29 Can we interface a 6264 to the 8088 chip which uses a 4MHz clock?

University of Tehran 30 Timing Requirements for 6264 SRAM TAVDV = ? TRLDV = ? TDVWH = ? TWHDX = ? TWLWH = ?

University of Tehran 31 HM6264B Series Read TIMING REQUIREMENTS

University of Tehran 32 HM6264B Series Write TIMING REQUIREMENTS

University of Tehran 33 HM6264B Series Read Timing Diagram

University of Tehran 34 HM6264B Series Write Timing Diagram

University of Tehran 35 Timing Requirements for 6264 SRAM TAVDV = t AA TRLDV = t OE TDVWH = t DW TWHDX = t DH TWLWH = t WP

University of Tehran 36 Timing Requirements for HM6264B-8L TAVDV = t AA = ? TRLDV = t OE = ? TDVWH = t DW = ? TWHDX = t DH = ? TWLWH = t WP = ?

University of Tehran 37 HM6264B Series Read TIMING REQUIREMENTS

University of Tehran 38 HM6264B Series Write TIMING REQUIREMENTS

University of Tehran 39 Timing Requirements for HM6264B-8L TAVDV = t AA = 85 ns TRLDV = t OE = 45 ns TDVWH = t DW = 40 ns TWHDX = t DH = 0 ns TWLWH = t WP = 55 ns

University of Tehran 40 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and HM6264B-8L

University of Tehran 41 Can we interface a 2764 to the 8088 chip which uses a 4MHz clock?

University of Tehran 42 Timing Requirements for 2764 EPROM TAVDV = ? TRLDV = ? TDVWH = ? TWHDX = ? TWLWH = ?

University of Tehran 43 M2764A Read Mode AC Characteristics

University of Tehran 44 M2764A Read Mode Timing Diagram

University of Tehran 45 Timing Requirements for 2764 EPROM TAVDV = t AVQV TRLDV = t GLQV TDVWH = N/A TWHDX = N/A TWLWH = N/A

University of Tehran 46 Timing Requirements for 2764 EPROM TAVDV = t AVQV = ? TRLDV = t GLQV = ? TDVWH = N/A TWHDX = N/A TWLWH = N/A

University of Tehran 47 M2764A Read Mode AC Characteristics

University of Tehran 48 Timing Requirements for M2764A-3 TAVDV = t AVQV = 180 ns TRLDV = t GLQV = 65 ns TDVWH = N/A TWHDX = N/A TWLWH = N/A

University of Tehran 49 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and M2764A-3

University of Tehran 50 What if we need to interface a “slow” memory to the 8088?

University of Tehran 51 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain “slow” memory chip

University of Tehran 52

University of Tehran 53 Recall:Write Pulse Width / Write-Time (TWLWH)

University of Tehran 54 Write Pulse Width / Write-Time (TWLWH) w/ 1 wait state

University of Tehran 55 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain memory chip caused by 1 wait state during a memory write on the “slow” memory chip

University of Tehran 56 How do we produce a wait state? By turning the READY input of the 8088 microprocessor to LOW

University of Tehran 57

University of Tehran 58 Requirements for the READY input of the 8088

University of Tehran 59 Requirements for the RDY of the 8284

University of Tehran 60

University of Tehran 61 Dynamic RAM Capacitor can hold charge Transistor acts as gate No charge is a 0 Can close switch & add charge to store a 1 Then open switch (disconnect) Can read by closing switch –Sense amps

University of Tehran 62 Hydraulic Analogy Storage Full (1) Empty (0) Pump fills tank to 1 value Pump drains tank to 0 value

University of Tehran 63 Reading Tank had a 1 value – raises water level Outside water begins at intermediate level (black wavy line) Tank had a 0 value – lowers water level

University of Tehran 64 DRAM Refreshing Refresh –Destructive read –Also, there’s steady leakage –Charge must be restored periodically

University of Tehran 65 DRAM Logical Diagram

University of Tehran 66 DRAM Read Signaling Lower pin count by using same pins for row and column addresses Delay until data available

University of Tehran 67 Standard DRAM Timing

University of Tehran 68 DRAM Write Timing

University of Tehran 69 PC RAM Interface

University of Tehran 70 DRAM Connections in PC

University of Tehran 71 Wait State Generation

University of Tehran 72 DRAM Refresh Many strategies Logic on chip Here a row counter

University of Tehran 73