1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)

Transistor Three terminal device Voltage between two terminals to control current flow in third terminal Versatile for many applications –Amplification –Memory –Logic –voltage controlled current source –switch Two popular types: –Bipolar Junction Transistor (BJT): used in power amplifier –MOSFET: used in integrated circuits

Enhancement-type NMOS transistor p-type material as substrate (i.e., body) n-type material chemically bonded on body at source and drain → source and drain are electrically indistinguishable Equivalent to having two diodes back to back → current cannot flow between source and drain Typical dimensions: o L = 0.1 to 3 μm, o W = 0.2 to 100 μm o t ox = 2 to 50 nm pn junction

Four terminals shown: Source (S), Gate (G), Drain (D) and Body (B). Body is typically grounded (along with one of the other three terminals) and does not play any role. Gate is electrically insulated from the body by Silicon Oxide (SiO 2 ) With no external voltages applied, normally there is no current between S and D. When certain voltage is applied at G, current flows from D to S. → The gate voltage controls the flow of current.

With S and D grounded, apply positive voltage to G (v GS > 0). Because G is electrically insulated to the body, in the channel, the gate voltage attracts electrons from the body. A thin layer of “induced n-type channel is formed between S and D. Across the induced n-type channel, there is no pn junction between S and D. The thickness of the induced n-type channel is proportional to v GS. Now, between S and D there is continuous n-type material. In the n-type region, there are excess electrons floating around (i.e., drift current flowing in random directions). Channel region

With v GS > 0, now apply small v DS > 0. Then, (diffusion) current starts flowing from D to S. There is no current flowing into G, because of SiO 2 insulator. To form an induced n-type channel sufficient to support current flow, v GS > V t. V t is called the threshold voltage.

For small v DS, i D is a linear function of v DS. The slope is the inverse of the resistance between D and S. When v GS < V t, the resistance is infinite

Increase v DS with fixed v GS > V t Voltage between G and S = v GS Voltage between G and D = v GS - v DS n-channel is thickest at S, and thinnest at D. As v DS increases, the resistance across the channel increases.

When v GS - v DS = V t, the channel depth at D is ≈ 0. Channel is then, “pinched off.” Increasing v DS beyond the point v DS = v GS - V t has no effect on i D. This region is called the saturation. v DSsat = v GS - V t Device in saturation: region v DS ≥ v DSsat Device in triode region: v DS < v DSsat

The above curves exist for each fixed value of v GS.

The PMOS transistor works similarly, but with n- type body and p-type S and D. To establish a p-type channel between S and D for the PMOS transistor v GS < V t where V t < 0. The current flows from S to D when v DS < 0. PMOS is not used by itself very often.

Complementary MOS (CMOS) Transistor Combines NMOS and PMOS on single substrate Most popular transistor for integrated circuit Very dense structure, consumes low power. Very powerful and versatile

Circuit Symbols for NMOS Most popular one to use

Triode Region v GS ≥ V t : channel is induces between S and D. v DS ≤ v GS - V t : channel is continuous (i.e., no pinch off).

Saturation Region v GS ≥ V t : channel is induces between S and D. v DS ≥ v GS - V t : channel is pinched off. At the boundary of triode and saturation: v DS = v GS - V t

i D - v GS relationship in saturation

Large Signal Circuit Model NMOS in Saturation

Voltage Characteristics for NMOS Transistor

More Accurate Model In saturation, slope in i D – v DS curve is not entirely flat. There is internal resistance, r o.

Large Signal Model for NMOS with r o

Circuit Symbols for PMOS Most popular one to use

Nominal Current Directions and Voltage Polarity Triode Region v GS ≤ V t : channel is induces between S and D where V t < 0. v DS ≥ v GS - V t : channel is continuous (i.e., no pinch off) where v DS < 0.

Voltage Characteristics for PMOS Transistor Skip All Sections for PMOS.

MOSFET Circuit with DC Inputs

MOSFET as Amplifier Utilize saturation mode. i D as function of v GS. Transconductance amplifier

Often, we want amplifiers to be linear. But i D is a quadratic function of v GS. Use DC biasing technique. Shift small signal around a point that mimics linearity. Common source amplifier

Q 1 is too close to cut-off and Q 2 is too close to triode boundary. We want the quiescent point to be in the middle of saturation region. For example, Q 3 may be a reasonable point. Boundary with triode region Q3Q3 Quiescent point is determined by V GS and R D.

Practical Methods of Biasing V G

Small Signal (or AC) Equivalent Models λ = 0λ ≠ 0 g m and r o are determined for each Q point. For analyzing small signal circuits, DC sources must be eliminated. Voltage source: short circuit Current source: open circuit

Given circuit → Small signal model

Source transform

Alternative Small Signal Models (T Models)

Basic Structure

Original Circuit

Equivalent Circuits

Next stage amplifier may present certain capacitance C. As a result of C, v O does not change instantly. Thus t PHL and t PLH are observed.

For every on-off cycle, Q N and Q P each consumes power equaling 0.5CV DD 2 where C is internal capacitance of transistors. Dynamic power dissipation P D = f CV DD 2 where f is the frequency of on-off cycle (i.e., clocking frequency)