1. CP 208 Digital Electronics Class Lecture 7 March 11, 2009

2. 2 MOS Field-Effect Transistors (MOSFETs)

3. In This Class We Will Continue to Discuss : Chap 4 MOS Field-Effect Transistors Following Topics: 4.2 Current-Voltage Characteristics 4.3 MOSFET Circuits at DC 4.4 MOSFET as an Amplifier & Switch 4.10 The CMOS Digital Logic Inverter BUT First: Home Work #2

4. Home Work No. 2 A logic inverter is implemented using the arrangement as shown in Figure above with switches having R on = 1 kΩ, and V DD = 5 V. If v I rises instantaneously from 0 V to 5 V and assuming the switches operate instantaneously — that is, at t = 0, PU opens and PD closes — find an expression for v O (t) assuming that a capacitance C = 1 pF is connected between output node and ground. Find high-to-low propagation delay (t PHL ). Repeat for v I falling instantaneously from 5V to 0V. Again assume that PD opens and PU closes instantaneously. Find expression for v O (t) and hence find t PLH. If switching frequency of the inverter is 100 MHz what would be the Dynamic Power Dissipated.

5. Solution: At t=0 PU opens, V across Cap. cannot Change Instantaneously.  at t=0+ the Output, v O (t 0+ ) = 5 V. Cap. discharges thru R on and Output Falls Exponentially to 0 V (ground).  v O (∞) = 0 V. Using the Output Eqn of STC Network for Step-function as I/P: y(t) = Y ∞ - ( Y ∞ - Y 0+ )e -t/τ v O (t) = v O (∞) – [v(∞) - v O (t 0+ ) ] e -t/τ v O (t) = 0 – (0 – 5) e -t/τ v O (t) = 5 e -t/τ _____ (1)

6. τ = RC. To Find t PHL … when t= t PHL v O (t=t PHL ) = 0.5(5+0) = 2.5 Eq (1) becomes: 2.5 = 5 e -tPHL /RC  e -tPHL /RC = 2.5 /5  e tPHL /RC = 5/2.5 = 2 Taking ln on both sides: t PHL / RC = ln (2) t PHL = 0.69xRxC = 0.69x1000x10 -12 = 0.69 n Sec

7. At t=0 PD opens, V across Cap. cannot Change Instantaneously.  at t=0+ Output v O (t 0+ ) = 0 V. Cap. Charges thru R on and Output Rises Exponentially to 5 V (V DD ).  v O (∞) = 5 V. Using the Output Eqn of STC Network for Step-function as I/P: y(t) = Y ∞ - ( Y ∞ - Y 0+ )e -t/τ v O (t) = v O (∞) – [v(∞) - v O (t 0+ ) ] e -t/τ v O (t) = 5 – (5 – 0) e -t/τ v O (t) = 5 – 5 e -t/τ _____ (2)

8. τ = RC. To Find t PLH … when t= t PLH v O (t=t PLH ) = 0.5(0+5) = 2.5 Eq (2) becomes: 2.5 = 5 – 5 e -tPLH /RC  5 e -tPLH /RC = 5 - 2.5  e tPLH /RC = 5/2.5 = 2 Taking ln on both sides: t PHL / RC = ln (2) t PHL = 0.69xRxC = 0.69x1000x10 -12 = 0.69 n Sec f = 100 MHz, V DD = 5 V C = 1x10 -12 farads P dynami = 100x10 6 x5 2 x 1x10 -12 P dynamic = 2.5 mW

9. About Mid-Term Exam … Will Include Following Topics: Representation of Analog Signal by Binary Digital Logic Inverters (General) Propagation Delay and Power Dissipation Diode Logic Gates Propagation Delay BJT as Amp and Switch (VTC) BJT Digital Logic Inverter Saturated vs non-saturated BJT MOSFET Physical Structure and Operation MOSFET as Switch CMOS Digital Logic Inverter and VTC Propagation Delay and Power Dissipation

13. 4.1.6 Derivation of the i D – v DS Relationship

15. 4.1.7 p-Channel MOSFET (PMOS) Fabricated on n-type substrate with p + regions for D and S and p-channel is induced under gate Operates same way as n- channel device except v GS, V t and v DS are negative Also, i D enters S and leaves D Because NMOS can be made smaller and operate faster and use lower supply voltage than PMOS, it has virtually replaced PMOS

16. 4.1.8 Complementary MOS or CMOS: 4.1.8 Complementary MOS or CMOS: In CMOS the NMOS is implemented in p-type substrate and PMOS transistor is formed in a separate n-type region, known as an n well. Separated by thick oxide. Also, as alternate an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

17. 4.2 Current-Voltage Characteristics 4.2.1 Circuit Symbol (a) Circuit symbol for the n-channel enhancement- type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant

18. Triode and Cutoff Regions are used as Switch and Saturation as Amplifier. Cutoff when v GS < V t Triode when v GS ≥ V t (Channel Induced) and v GD > V t (Channel Continuous)  v GS - v DS > V t {because v GD = v GS + v SD = v GS -v DS } then v DS < v GS – V t Saturation when v GD ≤ V t (Channel Pinched)  v DS ≥ v GS – V t 4.2.2 i D -v DS Characteristics

19. Triode: v GS ≥ V t (Channel Induced) v DS < v GS – V t (Channel Continuous) In words: n-channel MOSFET operates in Triode Region when v GS greater than V t and Drain voltage is Lower than Gate voltage by at least V t volts. Saturation: v GS ≥ V t (Channel Induced) v DS ≥ v GS – V t (Channel Pinched) In words: n-channel MOSFET operates in Saturation Region when v GS greater than V t and Drain voltage does not fall below Gate voltage by more than V t volts

20. (a) An n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D – v DS characteristics for a device with k’ n (W/L) = 1.0 mA/V 2.

22. The i D – v GS characteristic for an enhancement-type NMOS transistor in saturation (V t = 1 V, k’ n W/L = 1.0 mA/V 2 ).

23. Since the drain current is independent of drain voltage the Saturated MOSFET behaves as an ideal current source whose value is controlled by v GS. Large- signal Equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

24. Relative Levels of terminal Voltages of NMOS Transistor for Operation in the Triode and Saturation Regions

25. Exercise 4.4 and 4.5 4.4 : NMOS transistor with V t =0.7V has its source terminal grounded and a 1.5V dc applied to the gate. In what region does the device operate for (a) V D =+0.5 V? (b) V D =+0.9 V? (c) V D =+3 V? 4.5: If u n C ox =100 uA/V 2, W=10 um, L=1um, find the value of drain current that results in each of the three cases, (a), (b), and (c) above.

26. 4.2.4 p-Channel MOSFET Triode: v GS ≤ V t or v SG ≥ |V t | (Channel Induced) v DS ≥ v GS – V t (Channel Continuous) Saturation: v GS ≤ V t (Channel Induced) v DS ≤ v GS – V t (Channel Pinched)

27. Relative Levels of terminal Voltages of PMOS Transistor for operation in the Triode and Saturation Regions

28. 4.2.5 The Role of Substrate – Body Effect Usually S is Connected to B, which results in pn juction between substrate and channel (having a constant zero bias). In such case substrate/body does not play any role in ckt operation and it can be ignored.

29. 4.2.5 The Role of Substrate – Body Effect In ICs substrate is common to many MOS transistors, and is connected to most negative power supply (positive for PMOS). The reverse bias voltage will widen the depletion region at Source and reduce the channel depth. To return channel to its former state v GS has to be increased. Increasing Reverse Substrate Bias Voltage, V SB results in increase in V t as: 2 Φ f is typically 0.6 V and γ is fabrication-process parameter (or Body-effect Parameter). V BS gives rise to incremental change in V t, which in turn results in change in i D even when v GS is kept constant. Thus, body voltage behaves as another Gate.

30. Operation in Triode Region:

31. Operation in Saturation Region:

32. 4.3 MOSFET Circuits at DC Example 4.2: Design the ckt of Fig so that transistor operates at I D = 0.4mA and V D = +0.5 V. V t = 0.7, u n C ox = 100 uA/V 2, L = 1 um, W=32 um

33. Solution: V D = 0.5 V and V G = 0V V D > V G  NMOS operating in Saturation. Use saturation eqn of i D to find V GS : 400 = ½ x 100 x (32/1)x(V GS -V t ) 2 (V GS -V t ) = 0.5 V  V GS = 1.2 V Now V GS = V G +V S OR V S = V G -V GS V S = 0 -1.2 = - 1.2 V. R S = (V S -V SS )/I D = (-1.2 - (-2.5))/0.4 = 3.25 kΩ R D =(V DD -V D )/I D = (2.5 – 0.5)/0.4 = 5 k Ω

34. 4.4 MOSFET as an Amp and Switch MOSFET in Saturation Acts as a Voltage- Controlled Current Source Changes in Gate-to-Source Voltage v GS gives rise to i D Where v DS = v GS -V t

36. 4.4.1 The Transfer Characteristic Basic Circuit most commonly used for MOSFET Amplifier – Common Source or CS CKT Because grounded Source Terminal is Common for both Input and Output v GS = v I and controls i D Output v O is obtained in R D v O = v DS = V DD – i D R D OR i D = V DD /R D – v DS /R D Assume v I to be 0 to V DD we analyze ckt to determine output v O that is VTC of CS Amplifier

37. 4.4.2 Graphical Derivation of TC

39. 4.4.3 Operation as a Switch To use as Switch, the MOSFET is operated at the Extreme Points of the Transfer Curve Device is OFF for v I < V t and Operation is at Segment XA with v O = V DD Device is ON when v I is close V DD and operation is close to point C with v O very small, v O = V OC at point C Transfer Curve is similar to the form in Chap 1 for Digital Logic inverter MOSFET CKT can be used as Logic Inverter with ‘Low’ voltage Level close to 0V and ‘Hi’ level close to V DD

40. 4.10 The CMOS Digital Logic Inverter The Basic CMOS Inverter Utilizes two MATCHED enhancement type MOSFETS: Q N (n- channel) and Q P (p- channel) Body of each is connected to Source

42. 4.10.1 Circuit Operation Consider Two Extreme Cases v I = 0 (logic 0 level) and v I = V DD (logic 1 level). In both cases consider Q N is driving and Q P is Load (due to symmetry opposite will be identical)

45. 4.10.2 Voltage Transfer Characteristic (VTC)

46. 4.10.3 Dynamic Operation

48. 4.10.4 Current Flow and Power Dissipation

49. Home Work No. 4 (Due April 01, 2009) Problems at the End Of Chapter 4. 1.Problem 4.108 2.Problem 4.110 3.Problem 4.112 4.Problem 4.113

50. In Next Class We Will Continue to Discuss: Chap 4 MOS Field-Effect Transistors

51. How Boolean Logic Works http://computer.howstuffworks.com/boolean.htm Have you ever wondered how a computer can do something like balance a check book, or play chess, or spell-check a document? These are things that, just a few decades ago, only humans could do. Now computers do them with apparent ease. How can a "chip" made up of silicon and wires do something that seems like it requires human thought? If you want to understand the answer to this question down at the very core, the first thing you need to understand is something called Boolean logic.

52. Boolean logic, originally developed by George Boole in the mid 1800s, allows quite a few unexpected things to be mapped into bits and bytes. The great thing about Boolean logic is that, once you get the hang of things, Boolean logic (or at least the parts you need in order to understand the operations of computers) is outrageously simple. In this edition of HowStuffWorks we will first discuss simple logic "gates," and then see how to combine them into something useful bits and bytesHowStuffWorks