March 6, INST02, Novosibirsk1 Electronics for the e experiment at PSI Short introduction Trigger electronics DAQ electronics Slow Control For the MUEGAMMA collaboration Stefan Ritt (Paul Scherrer Institute, Switzerland)
March 6, INST02, Novosibirsk2 Search for e down to MEG Detector LFV Process forbidden by SM oscillations expected to enhance LFV rate Present limit: (MEGA) SUSY Theories: ~ LFV Process forbidden by SM oscillations expected to enhance LFV rate Present limit: (MEGA) SUSY Theories: ~ Required: stopping rate: 10 8 /s Resolutions (all FWHM): E e : 0.7% E : 52.8 MeV e : 12 mrad t e : 150ps Required: stopping rate: 10 8 /s Resolutions (all FWHM): E e : 0.7% E : 52.8 MeV e : 12 mrad t e : 150ps E e = 52.8 MeV Kinematics e = 180° E = 52.8 MeV e
March 6, INST02, Novosibirsk3 Detector Design Tests & Design Assembly Engineering Run Data taking m
March 6, INST02, Novosibirsk4 Status Large Prototype Currently largest LXe detector in (224 PMTs, 150l), Contains all critical parts of final detector Currently tested with 40 MeV ’s in Tsukuba, Japan First results in energy and position resolution expected next weeks
March 6, INST02, Novosibirsk5 Trigger Electronics
March 6, INST02, Novosibirsk6 Trigger Requirements Beam rate10 8 s -1 Fast LXe energy sum > 45MeV2 10 3 s -1 interaction point e + hit point in timing counter time correlation – e s -1 angular corrlation – e + 20 s -1 Beam rate10 8 s -1 Fast LXe energy sum > 45MeV2 10 3 s -1 interaction point e + hit point in timing counter time correlation – e s -1 angular corrlation – e + 20 s -1 E e = 52.8 MeV Kinematics e = 180° E = 52.8 MeV e M.C. Total ~800 PMTs Common noise contributes significantly to analog sum AC coupling Baseline drift How to evaluate of shower center? Total ~800 PMTs Common noise contributes significantly to analog sum AC coupling Baseline drift How to evaluate of shower center?
March 6, INST02, Novosibirsk7 Digital Trigger VME Interface (Cypress) 3.3V 2.5V LVDS FPGA SRAM LVDS FPGA SRAM LVDS Type2 LVDS Type1 8 channels clck, clear VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM LVDS 48 bits output 100MHz 10bit VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM LVDS 48 bits output 100MHz 10bit VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM LVDS 48 bits output 100MHz 10bit VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM LVDS 48 bits output 100MHz 10bit All PMTs in trigger Board hierarchy with LVDS interconnect Use FPGA with double capacity All PMTs in trigger Board hierarchy with LVDS interconnect Use FPGA with double capacity
March 6, INST02, Novosibirsk8 Latch Baseline Subtraction Baseline Subtraction Latch 10 bit 100 MHz Clock - + <thr + - Baseline Register Uses ~120 out of 5000 logic cells 8 channels/FPGA use 20% of chip Uses ~120 out of 5000 logic cells 8 channels/FPGA use 20% of chip Baseline subtracted signal LUT 10x10 Calibrated and linearized signal
March 6, INST02, Novosibirsk9 QT Algorithm original waveform smoothed and differentiated (Difference Of Samples) Threshold in DOS Region for pedestal evaluation integration area t Inspired by H1 Fast Track Trigger (A. Schöning) Hit region defined when Difference of Samples is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time Inspired by H1 Fast Track Trigger (A. Schöning) Hit region defined when Difference of Samples is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time 10ns
March 6, INST02, Novosibirsk10 Trigger latency BS Max T[ns] >45MeV e+ AND 10 stages = 1024 chn... ADC Inter-board communication: 120ns Total: 350ns (simulated) ~600 chn. / 10 bit At 100 MHz 75 GB/s processing power In 2 VME crates
March 6, INST02, Novosibirsk11 Prototype board ADC Signal- Generator DAC FPGA Trigger built by INFN, Pisa Fully simulated Trigger built by INFN, Pisa Fully simulated
March 6, INST02, Novosibirsk12 DAQ Electronics
March 6, INST02, Novosibirsk13 DAQ Hardware Requirements n E[MeV] ee t PMT sum e e e 51.5 MeV MeV ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed ~100ns ee
March 6, INST02, Novosibirsk14 Domino Sampling Chip Existing: 0.5 – 1.2 GHz sampling speed 128 sampling cells Readout at 5 MHz, 12 bit ~ 60 $/channel Needed: 2.5 GHz sampling speed Circular domino wave 1024 sampling cells 40 MHz readout < 100ps accuracy Existing: 0.5 – 1.2 GHz sampling speed 128 sampling cells Readout at 5 MHz, 12 bit ~ 60 $/channel Needed: 2.5 GHz sampling speed Circular domino wave 1024 sampling cells 40 MHz readout < 100ps accuracy C. Brönnimann et al., NIM A420 (1999) 264
March 6, INST02, Novosibirsk15 New Domino Ring Sampler (DRS) Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution 1024 bins 150ns waveform + 350ns delay Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution 1024 bins 150ns waveform + 350ns delay input
March 6, INST02, Novosibirsk16 DAQ Board 8 inputs trigger gate FADC 3 state switches FPGA SRAM shift register 9 channels 1024 bins / 40 MHz = 230 s acceptable dead time Zero suppression in FPGA QT Algorithm in FPGA (store waveform if multi-hit) Read out through VME or LVDS 9 channels 1024 bins / 40 MHz = 230 s acceptable dead time Zero suppression in FPGA QT Algorithm in FPGA (store waveform if multi-hit) Read out through VME or LVDS 40 MHz 12 bit VME Interface (Cypress) 3.3V 2.5V 8 channel DRS Trigger Input Board inter-connect FPGA SRAM FADC 8 channel DRS 8 channel DRS FADC 8 channel DRS Trigger BUS (2 nd level tr.) domino wave
March 6, INST02, Novosibirsk17 Status DRS Simulation finished in AMS 0.35 process Layout started Switch to 0.25 process First version summer ’02 Readout with trigger prototype board Costs per channel: ~25$ (board) + 6$ (chip)
March 6, INST02, Novosibirsk18 “Redefinition” of DAQ Conventional New AC couplingBaseline subtraction Const. Fract. Discriminator DOS – Zero crossing ADCNumerical Integration TDC Bin interpolation (LUT) Waveform Fitting Scaler (250 MHz)Scaler (50 MHz) OscilloscopeWaveform sampling 400 US$ / channel50 US$ / channel TDC Disc. ADC Scaler Scope FADC FPGA SRAM DSC ~GHz 100 MHz
March 6, INST02, Novosibirsk19 Slow Control Electronics
March 6, INST02, Novosibirsk20 Slow Control HV PC RS Temperature, pressure, … GPIB Valves ??? 15° C heater PLC 12: : : : : : : : MIDAS DAQ Ethernet Terminal Server
March 6, INST02, Novosibirsk21 Slow Control Bus HV Temperature, pressure, …Valves heater MIDAS DAQ
March 6, INST02, Novosibirsk22 Field Bus Solutions CAN, Profibus, LON available Node with ADC >100$ Interoperatibility not guaranteed Protocol overhead Local CPU? User programmable? How to integrate in HV? (CAEN use CAENET) CAN, Profibus, LON available Node with ADC >100$ Interoperatibility not guaranteed Protocol overhead Local CPU? User programmable? How to integrate in HV? (CAEN use CAENET)
March 6, INST02, Novosibirsk23 Generic Node ADuC812 / C8051F000 Micro controllers RS485 over flat ribbon Flat ribbon connector Power through bus Costs ~30$ Piggy back board ADuC812 / C8051F000 Micro controllers RS485 over flat ribbon Flat ribbon connector Power through bus Costs ~30$ Piggy back board
March 6, INST02, Novosibirsk24 2 versions Generic node with signal conditioning Sub-master with power supply and PC connection (Parallel Port, USB planned) Integration on sensors, in crates RS232 node planned BUS Oriented Crate Oriented 19” crate with custom backplane Generic node as piggy-back Cards for analog IO / digital IO / °C / 220V crate connects to parallel port (USB)
March 6, INST02, Novosibirsk25 Midas Slow Control Bus 256 nodes, nodes with one level of repeaters Bus length ~500m opto-isolated Boards for voltage, current, thermo couples, TTL IO, 220V output Readout speed: 0.3s for 1000 channels C library, command-line utility, Midas driver, LabView driver Nodes are “self-documenting” Configuration parameters in EEPROM on node Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) Nodes can be reprogrammed over network nodes, nodes with one level of repeaters Bus length ~500m opto-isolated Boards for voltage, current, thermo couples, TTL IO, 220V output Readout speed: 0.3s for 1000 channels C library, command-line utility, Midas driver, LabView driver Nodes are “self-documenting” Configuration parameters in EEPROM on node Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) Nodes can be reprogrammed over network
March 6, INST02, Novosibirsk26 High Voltage System C node Opto-couplers External HV
March 6, INST02, Novosibirsk27 HV performance Regulates common HV source V, ~1mA DAC 16bit, ADC 14bit Current trip ~10 s Self-calibration with two high accuracy reference voltages Accuracy <0.3V absolute Boards with 12 channels, crates with 192 channels 30$/channel (+ext. HV) Regulates common HV source V, ~1mA DAC 16bit, ADC 14bit Current trip ~10 s Self-calibration with two high accuracy reference voltages Accuracy <0.3V absolute Boards with 12 channels, crates with 192 channels 30$/channel (+ext. HV) Prototype
March 6, INST02, Novosibirsk28 Conclusions FPGA-based trigger with 100MHz FADC designed 2 GHz waveform sampling on all channels planned HV system with 0.3V accuracy designed New slow control system (30$/node, 300 s readout) Transition prototype series Physics runs in 2005 Can be useful for other experiments In case of interest: FPGA-based trigger with 100MHz FADC designed 2 GHz waveform sampling on all channels planned HV system with 0.3V accuracy designed New slow control system (30$/node, 300 s readout) Transition prototype series Physics runs in 2005 Can be useful for other experiments In case of interest: Transparencies on Muegamma Web Site: