ECE 448 Lecture 6 FPGA devices ECE 448 – FPGA and ASIC Design with VHDL

Required reading (1) S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 3.6.5 Field-Programmable Gate Arrays ECE 448 – FPGA and ASIC Design with VHDL

Required Reading (2) Xilinx, Inc. Spartan-3 FPGA Introduction Features Architectural Overview Package Marking Spartan-3 FPGA Functional Description CLB Overview, Block RAM Overview Dedicated Multipliers Interconnect ECE 448 – FPGA and ASIC Design with VHDL

World of Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable SPLD CPLD FPGA PAL PLA PML LUT (Look-Up Table) MUX Gates ECE 448 – FPGA and ASIC Design with VHDL

Two competing implementation approaches FPGA Field Programmable Gate Array ASIC Application Specific Integrated Circuit designed all the way from behavioral description to physical layout no physical layout design; design ends with a bitstream used to configure a device designs must be sent for expensive and time consuming fabrication in semiconductor foundry bought off the shelf and reconfigured by designers themselves ECE 448 – FPGA and ASIC Design with VHDL

What is an FPGA? Configurable Logic Blocks I/O Blocks Block RAMs ECE 448 – FPGA and ASIC Design with VHDL

Which Way to Go? ASICs FPGAs Off-the-shelf High performance Low development cost Low power Short time to market Low cost in high volumes Reconfigurability ECE 448 – FPGA and ASIC Design with VHDL

Other FPGA Advantages Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits Easy upgrades like in case of software Unique applications reconfigurable computing ECE 448 – FPGA and ASIC Design with VHDL

Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. Atmel Lattice Semiconductor Flash & antifuse FPGAs Actel Corp. Quick Logic Corp. Share over 60% of the market ECE 448 – FPGA and ASIC Design with VHDL

ISE Alliance and Foundation Series Design Software Xilinx Primary products: FPGAs and the associated CAD software Main headquarters in San Jose, CA Fabless* Semiconductor and Software Company UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} Seiko Epson (Japan) TSMC (Taiwan) Programmable Logic Devices ISE Alliance and Foundation Series Design Software ECE 448 – FPGA and ASIC Design with VHDL

Xilinx FPGA Families Old families High-performance families XC3000, XC4000, XC5200 Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. High-performance families Virtex (0.22µm) Virtex-E, Virtex-EM (0.18µm) Virtex-II, Virtex-II PRO (0.13µm) Virtex-4 (0.09µm) Low Cost Family Spartan/XL – derived from XC4000 Spartan-II – derived from Virtex Spartan-IIE – derived from Virtex-E Spartan-3 ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL

Spartan-3 Family General Architecture ECE 448 – FPGA and ASIC Design with VHDL

CLB Structure ECE 448 – FPGA and ASIC Design with VHDL

CLB Structure ECE 448 – FPGA and ASIC Design with VHDL The configurable logic block (CLB) contains two slices. Each slice contains two 4-input look-up tables (LUT), carry & control logic and two registers. There are two 3-state buffers associated with each CLB, that can be accessed by all the outputs of a CLB. Xilinx is the only major FPGA vendor that provides dedicated resources for on-chip 3-state bussing. This feature can increase the performance and lower the CLB utilization for wide multiplex functions. The Xilinx internal bus can also be extended off chip. ECE 448 – FPGA and ASIC Design with VHDL

CLB Slice Structure Each slice contains two sets of the following: Four-input LUT Any 4-input logic function, or 16-bit x 1 sync RAM (SLICEM only) or 16-bit shift register (SLICEM only) Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control Two slices form a CLB. These slices can be used independently or together for wider logic functions.Within each slice also, the LUT and the flip flop can be used for the same function or for independent functions. The flip flops do not handcuff the designers into only having a set or clear. And for more ASIC like flows, the flip flop can be sued as latch. So, the designers do not need to re-code the design for the device architecture. ECE 448 – FPGA and ASIC Design with VHDL

LUT (Look-Up Table) Functionality Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs ECE 448 – FPGA and ASIC Design with VHDL

5-Input Functions implemented using two LUTs One CLB Slice can implement any function of 5 inputs Logic function is partitioned between two LUTs F5 multiplexer selects LUT ECE 448 – FPGA and ASIC Design with VHDL

5-Input Functions implemented using two LUTs OUT LUT ECE 448 – FPGA and ASIC Design with VHDL

Distributed RAM = or CLB LUT configurable as Distributed RAM RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S A4 RAM16X2S O1 D0 D1 O0 = LUT or RAM16X1D SPO DPRA0 DPO DPRA1 DPRA2 DPRA3 CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual-Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions. ECE 448 – FPGA and ASIC Design with VHDL

Shift Register = Each LUT can be configured as shift register Q CE LUT IN CLK DEPTH[3:0] OUT = Each LUT can be configured as shift register Serial in, serial out Dynamically addressable delay up to 16 cycles For programmable pipeline Cascade for greater cycle delays Use CLB flip-flops to add depth The LUT can be configured as a shift register (serial in, serial out) with bit width programmable from 1 to 16. For example, DEPTH[3:0] = 0010(binary) means that the shift register is 3-bit wide. In the simplest case, a 16 bit shift register can be implemented in a LUT, eliminating the need for 16 flip flops, and also eliminating extra routing resources that would have been lowered the performance otherwise. ECE 448 – FPGA and ASIC Design with VHDL

Shift Register Register-rich FPGA 64 Operation A 4 Cycles 8 Cycles Operation B 3 Cycles Operation C 12 Cycles 9-Cycle imbalance Register-rich FPGA Allows for addition of pipeline stages to increase throughput Data paths must be balanced to keep desired functionality In this example, there is a cycle imbalance, which must be fixed. Let’s think of how the shift register can fix the imbalanced cycles. As seen from the slide, the logic will be off by nine clock cycles. ECE 448 – FPGA and ASIC Design with VHDL

Carry & Control Logic SLICE ECE 448 – FPGA and ASIC Design with VHDL COUT YB Look-Up Table Carry & Control Logic Y G4 G3 G2 G1 S D Q O CK EC R F5IN BY SR XB Look-Up Table Carry & Control Logic X S F4 F3 F2 F1 D Q O The configurable logic block (CLB) contains two slices. Each slice contains two 4-input look-up tables (LUT), carry & control logic and two registers. There are two 3-state buffers associated with each CLB, that can be accessed by all the outputs of a CLB. Xilinx is the only major FPGA vendor that provides dedicated resources for on-chip 3-state bussing. This feature can increase the performance and lower the CLB utilization for wide multiplex functions. The Xilinx internal bus can also be extended off chip. CK EC R CIN CLK CE SLICE ECE 448 – FPGA and ASIC Design with VHDL

Fast Carry Logic Each CLB contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Carry logic is independent of normal logic and routing resources MSB Carry Logic Routing LSB ECE 448 – FPGA and ASIC Design with VHDL

Accessing Carry Logic All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then…) Counters (count <= count +1) ECE 448 – FPGA and ASIC Design with VHDL

Block RAM (BRAM) ECE 448 – FPGA and ASIC Design with VHDL

Block RAM Most efficient memory implementation Spartan-3 Dual-Port Port A Port B Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements 4 to 104 memory blocks 18 kbits = 18,432 bits per block (16 k without parity bits) Use multiple blocks for larger memories Builds both single and true dual-port RAMs The Block Ram is true dual port, which means it has 2 independent Read and Write ports and these ports can be read and/or written simultaneously, independent of each other. All control logic is implemented within the RAM so no additional CLB logic is required to implement dual port configuration. The Altera 10KE and ACEX 1K families have only 2-port RAM. To emulate dual port capability, they would need twice the number of memory blocks and at half the performance. ECE 448 – FPGA and ASIC Design with VHDL

Spartan-3 Block RAM Amounts ECE 448 – FPGA and ASIC Design with VHDL

Positions of Block RAM Columns ECE 448 – FPGA and ASIC Design with VHDL

Block RAM Port Aspect Ratios 1 2 4 4k x 4 8k x 2 4,095 16k x 1 8,191 8+1 2k x (8+1) 2047 16+2 1024 x (16+2) 1023 16,383 ECE 448 – FPGA and ASIC Design with VHDL

Block RAM Port Aspect Ratios ECE 448 – FPGA and ASIC Design with VHDL

Single-Port Block RAM ECE 448 – FPGA and ASIC Design with VHDL

Dual-Port Block RAM ECE 448 – FPGA and ASIC Design with VHDL

Dual-Port Bus Flexibility RAMB4_S16_S8 WEA Port A In 1K-Bit Depth Port A Out 18-Bit Width ENA RSTA DOA[17:0] CLKA ADDRA[9:0] DIA[17:0] WEB Port B Out 9-Bit Width Port B In 2k-Bit Depth ENB RSTB DOB[8:0] CLKB ADDRB[10:0] Because the RAM blocks are true dual port, each port can be configured for a different width. This example shows port A configured as 1K x 4 and port B configured as 256 x16. This feature can be used for applications requiring different bus widths for two applications. Note that the Altera FLEX 10K and ACEX 1K families do not have this feature, as they do not have true dual port capability. DIB[8:0] Each port can be configured with a different data bus width Provides easy data width conversion without any additional logic ECE 448 – FPGA and ASIC Design with VHDL

Two Independent Single-Port RAMs RAMB4_S1_S1 Port A In 8K-Bit Depth DOA[0] DOB[0] WEA ENA RSTA ADDRA[12:0] CLKA DIA[0] WEB ENB RSTB ADDRB[12:0] CLKB DIB[0] Port A Out 1-Bit Width 0, ADDR[12:0] Port B In 8K-Bit Depth Port B Out 1-Bit Width 1, ADDR[12:0] Here, a single 4K bit memory block is split into two independent 2K bit Single-Port blocks. This feature allows efficient utilization of memory bits. The upper 2K bit block is accessed by tying the ADDR11 bit to Vcc whereas the lower 2K bit block is accessed by tying it to GND instead. To access the lower RAM Tie the MSB address bit to Logic Low To access the upper RAM Tie the MSB address bit to Logic High Added advantage of True Dual-Port No wasted RAM Bits Can split a Dual-Port 16K RAM into two Single-Port 8K RAM Simultaneous independent access to each RAM ECE 448 – FPGA and ASIC Design with VHDL

Block RAM Waveforms – WRITE_FIRST ECE 448 – FPGA and ASIC Design with VHDL

Block RAM Waveforms – READ_FIRST ECE 448 – FPGA and ASIC Design with VHDL

Block RAM Waveforms – NO_CHANGE ECE 448 – FPGA and ASIC Design with VHDL

Embedded Multipliers ECE 448 – FPGA and ASIC Design with VHDL

18 x 18 Embedded Multiplier Fast arithmetic functions Optimized to implement multiply / accumulate modules ECE 448 – FPGA and ASIC Design with VHDL

18 x 18 Multiplier Embedded 18-bit x 18-bit multiplier 2’s complement signed operation Multipliers are organized in columns 18 x 18 Multiplier Output (36 bits) Data_A (18 bits) Data_B ECE 448 – FPGA and ASIC Design with VHDL

Positions of Multipliers ECE 448 – FPGA and ASIC Design with VHDL

Asynchronous 18-bit Multiplier ECE 448 – FPGA and ASIC Design with VHDL

18-bit Multiplier with Register ECE 448 – FPGA and ASIC Design with VHDL

Input/Output Blocks (IOBs) ECE 448 – FPGA and ASIC Design with VHDL

Basic I/O Block Structure Three-State D Q FF Enable EC Three-State Control Clock SR Set/Reset Output D Q FF Enable EC Output Path SR Direct Input FF Enable Input Path Registered Input Q D EC SR ECE 448 – FPGA and ASIC Design with VHDL

IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed ECE 448 – FPGA and ASIC Design with VHDL

Routing Resources ECE 448 – FPGA and ASIC Design with VHDL

Routing Resources PSM Programmable Switch Matrix CLB ECE 448 – FPGA and ASIC Design with VHDL

Long and Hex Lines ECE 448 – FPGA and ASIC Design with VHDL

Double and Direct Lines ECE 448 – FPGA and ASIC Design with VHDL

Spartan-3 Family Attributes ECE 448 – FPGA and ASIC Design with VHDL

Spartan-3 FPGA Family Members ECE 448 – FPGA and ASIC Design with VHDL

FPGA Nomenclature ECE 448 – FPGA and ASIC Design with VHDL

Device Part Marking We’re Using: XC3S100-4FG256 ECE 448 – FPGA and ASIC Design with VHDL