DIGITAL ELECTRONICS WORKSHOP Sequential Logic Circuits Sunday, 20 July Pn. Norina Idris, PPK Mikroelektronik, UniMAP

“Combinational” vs “Sequential” Combinational – outputs depend only on the inputs. Do not have memory. Cannot store state. Sequential – outputs depend on inputs and past behavior. Require use of storage elements. Contents of storage elements is called “state”. Circuit goes through sequence of states as a result of changes in inputs.

Overview of Sequential Circuits Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams

Block Diagram of a Sequential Circuit

Sequential Circuit - Basic Function The data stored in the “storage elements” defines the “state” of the sequential circuit at that time, i.e. present state. The inputs, together with the present state of the storage elements, determine the outputs and the next state of the storage elements.

Types of Sequential Circuits Depends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous!

Synchronous Clocked Sequential Circuit

Simple Memory Structure

Another Structure for Memory Reset Set Q

The Most Common Memory Elements Used Latches Flip-flops The basic single-bit memory elements, With one or two inputs/outputs, Designed using individual logic gates and feedback loops. Both are referred to as “bistable elements” or “multivibrator”, i.e. having two stable states.

Part I Latches & Flip-flops

Latch vs Flip-flop Latch Asynchronous. “The inputs, together with the present state of the storage elements, determine the outputs and the next state of the storage elements.” Latch Asynchronous. Change of state can happen at any time, whenever its inputs change. Flip-Flops Synchronous. Change of state occurs only at specific times determined by a clock pulse input. Flip-flops are constructed from latches!!

Types of Latches SR Latch Gated D Latch S R Latch Q C R Gated SR Latch (with control)

S R Latch

SR Latch with NOR Gates Q Reset Set Q Re-drawn …

SR Latch Function Table Hold Hold

… SR Latch Operation If S=R=0 => the latch is either SET or reSET.. If S=R=1 => both Q and NQ = 0. Undefined State!! … violation of Q vs NQ.

Simulation of SR Latch .. with delay

S-R Latch vs S-R Latch

S R Latch

S R Latch with NAND Gates Q Active-LOW SR Latch …

SR Latch Function Table Hold Hold

S R Latch Function Table

S R Latch Waveform 1 2 3 4 5 6 7 Assume that Q is initially LOW

Gated SR Latch = SR latch with Control input Q C R C or Enable or CLock = SR latch with Control input = SR latch with Enable input = Clocked SR Latch

Gated S-R Latch - Basic Operation A gate input is added to the S-R latch to: - Act as a “control” input. Make the latch synchronous. Control=1 => Latch can change state Control =0 => Latch “holds” previous value

Gated SR Latch Function Table Where is the additional circuit?

Gated SR Latch Simulation Q C R R C Q S 1 Time ?

Gated D Latch D Q C

Gated D Latch Add inverter to the SR latch…

Gated D Latch Function Table Note: There are no “indeterminate states” …

Gated D Latch Simulation 1 2 3 4 Time Clk D Q

State Change in Latch Change in latch state => Trigger The D latch with clock pulses on its Control, C, input is triggered every time a pulse to logic-1 level occurs. As long as the pulse remains at the logic-1 level, any changes in the data input will change the state of the latch. “Level” triggered

Edge-Triggered Flip-flops Flip-flops are synchronous bistable devices. Synchronous: because the output changes state ony at a certain point on a triggering input, i.e. CLK, which is the control input. Edge-triggered flip-flop: changes state at either the positive edge (rising edge) or at the negative edge (falling edge) of the cock pulse.

Clock Signals & Synchronous Sequential Circuits Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock signal Clock Cycle Time 1 A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

Edge-triggered Flip-flop Symbols Positive edge triggered and Negative edge-triggered All the above flip-flops have the triggering input called clock (CLK/C)

Edge-Triggered Flip-flops SR flip-flop JK flip-flop D flip-flop T flip-flop

Timing Diagram

Negative-Edge Triggered D Flip-Flop The edge-triggered D flip-flop is the same as the master- slave D flip-flop. It can be formed by: Replacing the first clocked S-R latch with a clocked D latch or Adding a D input and inverter to a master-slave S-R flip-flop The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputs The change of the D flip-flop output is associated with the negative edge at the end of the pulse. It is called a negative-edge triggered flip-flop C S R Q D

Positive-Edge Triggered D Flip-Flop Formed by adding inverter to clock input Q changes to the value on D applied at the positive clock edge within timing constraints to be specified. The standard flip-flop used for most sequential circuits. C S R Q D D Q Clock

Positive-Edge-Triggered D Flip-Flop 1 P3 P1 2 5 Q Clock D Q (b) Graphical symbol Clock P2 6 Q 3 4 P4 D (a) Circuit

A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

Timing Diagram

Positive-Edge Triggered JK Flip-Flop Not used much anymore in VLSI Advantageous only if using FF chips J D Q Q K Q Q Clock (a) Circuit J K Q ( t + 1 ) Q ( t ) J Q 1 1 1 K Q 1 1 Q ( t ) (b) Truth table (c) Graphical symbol

Function Table for JK Flip Flop J K CLK Q Q’ 0 0 Q0 Q0’ Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 Q0’ Q0 Toggle (opposite state)

Timing Diagram: Positive-Edge Triggered

Timing Diagram: Negative-Edge Triggered

T Flip-Flop Useful in counters Not available in IC form T Latches do not exist T Q ( t + 1 ) Q ( t ) 1 Q ( t ) (b) Truth table D Q T Clock (a) Circuit T Q Q (c) Graphical symbol

T Flip-Flop Clock T Q (d) Timing diagram

D latch vs D flip-flop

D Latch versus D Flip-Flop Q Q a D Clock Q a b c Clock Clk Q Q a D Q Q b Q Q b D Q Q c Q Q c (a) Circuit (b) Timing diagram Comparison of level-sensitive and edge-triggered devices

Standard Graphic Symbols for Latch and Flip-Flops Complete the list !! T T

Direct Inputs Preset (Set) & Clear (ReSet)

Clear and Preset Inputs Set/Reset independent of clock Direct set or preset Direct reset or clear Often used for power-up reset Preset Q Preset Clock D Q Q Q Clear D (b) Graphical symbol Clear (a) Circuit

Example: D-FF with Direct Set and Reset

Direct Inputs At power up or at reset, all or part of a sequential circuit usually is initialized to a known state before it begins operation This initialization is often done outside of the clocked behavior of the circuit, i.e., asynchronously. Direct R and/or S inputs that control the state of the latches within the flip-flops are used for this initialization. For the example flip-flop shown 0 applied to R resets the flip-flop to the 0 state 0 applied to S sets the flip-flop to the 1 state D C S R Q

J-K flip-flop with active-LOW Preset and Clear inputs

Timing Diagram

State Diagram, Function Table, Excitation Table, Characteristic Equation

State Diagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input values which causes the state transition, and A label: On each circle with the output value produced, or On each directed arc with the output value produced.

4- bit Binary Counter Counts from 0000 (0H) to 1111 (FH) State Diagram Example 4- bit Binary Counter Counts from 0000 (0H) to 1111 (FH)

Detailed Function Table SR Latch SR 1 SR 0X 10 X0 01 00 01 11 10 X 1 Q Detailed Function Table S R Q Q+ 1 X Characteristic Equation: Q+ = S + R’Q Excitation Table Q Q+ S R X 1 State Transition Diagram: The excitation table in graphical form Excitation Table: What are the necessary inputs to cause a particular kind of change in state?

Detailed Function Table D Latch D 1 1 Q Detailed Function Table D Q Q+ 1 Characteristic Equation Q+ = D Excitation Table Q Q+ D 1 State Transition Diagram

Detailed Function Table JK Flip-Flop 00 01 11 10 1 JK 1 JK 0X 1X X0 X1 Q Detailed Function Table J K Q Q+ 1 Characteristic Equation Q+ = JQ’ + K’Q Excitation Table Q Q+ J K X 1 State Transition Diagram

Detailed Function Table T Flip-Flop T 1 1 Q Detailed Function Table T Q Q+ 1 Characteristic Equation Q+ = T’Q + TQ’ = T  Q Excitation Table Q Q+ D 1 State Transition Diagram

Which Flip-flop to use ..?

Choosing a Flip-Flop SR Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, is the fundamental building block of other flip-flop types D Flip-flop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers JK Flip-flop: versatile building block: can be used to implement D and T FFs usually requires least amount of logic to control Q+ however, has two inputs with increased wiring complexity T Flip-flop: doesn't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!!

Characteristic Equation & Excitation Table Summary Device Type Characteristic Equation SR latch Q+ = S + R’Q D latch Q+ = D JK flip-flop Q+ = JQ’ + K’Q T flip-flop Q+ = TQ’ + T’Q Q Q+ S R D J K T X 1

Let’s Recap…

Standard Graphic Symbols for Latch and Flip-Flops

Flip-Flop Characteristic Table

Flip-Flop Excitation Tables

Flip-flop Applications Parallel Data Storage Frequency Divider Counter Shift Registers

Parallel Data Storage –using Registers 4-bit REGISTER

Frequency Divider: Divide-by-2 Q is one-half the frequency of CLK

Frequency Divider: Divide-by-4

Counter : 00, 01, 10, 11 2-bit Counter

Part II Shift Registers

Shift Registers Topics Basic shift register function Serial in / serial out shift registers Serial in / parallel out shift registers Parallel in / serial out shift registers Parallel in / parallel out shift registers Bidirectional shift registers Shift register applications

rEgIStERs… What are they?

Registers … deFiniTioN Registers – used for storing & manipulating data. Register = Daftar Shift Register = Daftar Anjakan Loading (Pembebanan) – is the transfer of information into a register. Load = Beban

Registers.. deFiniTioN A register is a memory device that can be used to store more than one-bit of information. A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register.

n-bit Register An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits. Example: 74LS175 4-bit register 74LS175 1D 1Q D Q CLR Q /1Q CLK CLR 4Q 3Q 2Q 1Q 74LS175 1D 2D 3D 4D 2Q 2D D Q CLR Q /2Q 3Q 3D D Q CLR Q /3Q 4Q 4D D Q CLR Q /4Q CLK /CLR

Shift Registers …? A register capable of shifting its stored data, in both directions. Consists of a chain of FFs in cascade. The output of one FF goes into the input of the next FF. The shift from one stage to the next is dependent on a common clock pulse.

A 4-Bit Shift Register … Serial output So

… 4-bit Shift Register SI, serial input, is the input to the leftmost FF during the shift. SO, serial output, is taken from the rightmost FF.

Shift Registers Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) Shift Left is towards MSB 0 1 1 1 LSI Q3 Q2 Q1 Q0 1 1 1 LSI Q3 Q2 Q1 Q0 Shift Right (or Shift ?Up? ) is towards LSB RSI 0 1 1 1 Q3 Q2 Q1 Q0 RSI 0 1 1 Q3 Q2 Q1 Q0

Basic Shift Register Functions Consist of an arrangement of flip-flops Important in applications involving storage and transfer of data (data movement) in digital system Used for storing and shifting data (1s and 0s) entered into it from an external source and possesses no characteristic internal sequence of states. D flip-flops are use to store and move data

The flip-flop as a storage element Still remember the truth table for D flip flop? D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

The flip-flop as a storage element When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

Types of Shift Register Serial In / Serial Out Shift Registers (SISO) Serial In /Parallel Out Shift Registers (SIPO) Parallel In / Serial Out Shift Registers (PISO) Parallel In / Parallel Out Shift Registers (PIPO)

Basic data movement in shift registers (Four bits are used for illustration. The bits move in the direction of the arrows.)

Serial In, Serial Out Shift Register (SISO) SRG n > SI SO D Q CLK · SERIN CLOCK SEROUT For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 serout: - - - - 1 0 1 1 0 0 clock:

Serial In, Serial Out Shift Register (SISO)

1010 Four bits (1010) being entered serially into the register.

Serial In, Serial Out Shift Register (SISO) FF0 FF1 FF2 FF3 Clear 1010 101 10 1 00 000 0000

Four bits (1010) being serially shifted out of the register and replaced by all zeros.

Serial In, Parallel Out Shift register (SIPO) SRG n > SI 1Q · 2Q nQ D Q CLK · SERIN CLOCK nQ 2Q 1Q (SO) Serial to Parallel Converter Example: 4-bit shift register serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 1 0 1 1 0 0 1 1 1 2Q: - - 1 0 1 1 0 0 1 1 3Q: - - - 1 0 1 1 0 0 1 4Q: - - - - 1 0 1 1 0 0 clock:

Can u see the difference? D Q CLK · SERIN CLOCK SERIAL OUT D Q CLK · SERIN CLOCK nQ 2Q 1Q PARALLEL OUT

Serial In, Parallel Out Shift register (SIPO) Data bits entered serially (right-most bit first) Difference from SISO is the way data bits are taken out of the register – in parallel. Output of each stage is available

Example : The states of 4-bit register (SRG 4) for the data input and clocks waveforms. Assume the register initially contains all 1s

4-bit parallel in/serial out shift register (PISO)

4-bit parallel in/serial out shift register (PISO)

Parallel In, Serial Out Shift Register (PISO) CLOCK LOAD/SHIFT SERIN 1Q S D Q CLK 1D L 2Q S D Q CLK 2D L Parallel to Serial Converter Load/Shift=1 Di Qi Load/Shift=0 Qi Qi+1 · · · NQ S D Q CLK SEROUT ND L

Parallel In, Parallel Out Shift Register (PIPO) Immediately following simultaneous entry of all data bits, it appear on parallel output.

Parallel In, Parallel Out Shift Register (PIPO) CLOCK LOAD/SHIFT SERIN S D Q CLK 1Q 1D L S D Q CLK 2Q 2D L General Purpose: Makes any kind of (left) shift register · · · S D Q CLK NQ ND L

Bi-directional Shift Registers Data can be shifted left AnD right … A parallel load may be possible

Bi-directional Universal Shift Registers 4-bit Bi-directional Universal (4-bit) PIPO CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN 11 1 10 9 7 6 4 5 3 2 12 13 14 15 74x194 Modes: Hold Load Shift Right Shift Left R L Mode Next state Function S1 S0 QA* QB* QC* QD* Hold 0 0 QA QB QC QD Shift right/up 0 1 RIN QA QB QC Shift left/down 1 0 QB QC QD LIN Load 1 1 A B C D

Shift Register Applications Counter – Johnson, Ring State Registers Serial Interconnection of Systems Bit Serial Operations Time-delay Device

Four-bit Johnson counters Serial output connected back toserial input The complement of the output (Q’) is fedback into 1st FF.

A 10-bit ring counter Assume initial state : 0000000101

More Shift Register Applications State Registers Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position (i.e. a finite memory machine) Very effective for sequence detectors Serial Interconnection of Systems keep interconnection cost low with serial interconnect

More Shift Register Applications Bit Serial Operations Bit serial operations can be performed quickly through device iteration Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc). A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

More Shift Register Applications Example: Serial Interconnection of Systems CLOCK Transmitter Receiver Control Circuits Control Circuits /SYNC Parallel Data from A-to-D converter Parallel Data to D-to-A converter Serial-to-parallel converter Parallel-to-serial converter Serial DATA n One bit n

More Shift Register Applications Example: The shift register as a time-delay device

Part III Counters

Standard Graphic Symbols for Latch and Flip-Flops

Flip-Flop Characteristic Table

Flip-Flop Excitation Tables

Counters - Definition A counter is: A register that “counts” through a specific sequence of states upon the application of a sequence of input pulses e.g. clock or other signals. Counters can count up, count down, or count through other fixed sequences.

Binary Counter An n-bit binary counter: Consists of n flip-flops. Counts from 0 to (2n -1).

Two Counter Categories Synchronous counter Ripple counters (Asynchronous counter)

… Counters Ripple Counters (Asynchronous Counters) FF output transition serves as a source for triggering other FFs. C input not triggered by the common clock pulse. Synchronous Counters C inputs of all FFs receive the common clock pulse. The change of state is determined from the present state of the counter.

Counter Examples Binary Counter Decade Counter/BCD Counter Gray-Code Counter Modulus Counter Up-Down Counter Arbitrary Sequence Counter Johnson Counter Ring Counter

Synchronous Counters

Synchronous Counters The clk inputs of all flip-flops receive a common clock pulse (directly connected). The change of state is determined from the present state. By using combinational logic.

4-bit Synchronous Binary Counter

Johnson Counter The complement of the output of the last flip-flop is connected back to the input of the first flip-flop. The counter will “fill up” with 1’s from left to right, and then will “fill up” with 0’s again

Figure 9–24 Timing sequence for a 4-bit Johnson counter. Convert the waveform results into table form. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Ring Counter A “1” is always retained in the counter and simply shifted “around the ring”, advancing one stage for each clock pulse.

Output of 10-bit Ring Counter Initial state is 1010 0000 00 Convert the waveform results into table form.

Asynchronous Counters

Ripple Counters – clk Source The clk inputs of some flip-flops are supplied by the outputs on other flip-flops. The (Master) CLOCK is connected to the clk input on the LSB bit flip-flop. For all other bits, a flip-flop output is connected to the clock input, Thus, the circuit is not synchronous.

Ripple Counters – Pros & Cons Advantage Simple Hardware (Decoder gates not required). Low power consumption. Disadvantage Slow Output change is delayed more for each bit towards the MSB.

4-Bit Ripple Counter Both J and K inputs of the flip-flops are tied to logic 1 flip-flop complements

5-4 Ripple Counters Figure 5-8 J and K of all FFs – tied together to logic 1 Negative edge triggered clock inputs. Q0 serves as clock input to 2nd FF, and so on. N(Clear) – clears registers to 0 asynchronously.

SEQUENTIAL CIRCUITS Design Examples Using Flip-flops

Example 1 Input: x(t) Output: y(t) State: (A(t), B(t)) What is the Output Function? What is the Next State Function? A C D Q y x B CP

Example 1 Boolean equations for the functions: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A(t)x(t) y(t) = x(t)(B(t) + A(t)) x D Q A C Q A Next State D Q B CP C Q' y Output

State Table Characteristics State table – a multiple variable table with the following four sections: Present State – the values of the state variables for each allowed state. Input – the input combinations allowed. Next-state – the value of the state at time (t+1) based on the present state and the input. Output – the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present State and the outputs are Output, Next State

Example 1: State Table The state table can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t) 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 1 1

Example 2: Alternative State Table 2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) Present State Next State x(t)=0 x(t)=1 Output x(t)=0 x(t)=1 A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t) 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0

Design of Synchronous Binary Counters Using D flip-fops Using JK flip-flops

Detailed Function Table D Latch D 1 1 Q Detailed Function Table D Q Q+ 1 Characteristic Equation Q+ = D Excitation Table Q Q+ D 1 State Transition Diagram

Counting Sequence of a 4-bit Binary Counter

4-bit Binary Counter Using D flip-flop

State Table and Flip-Flop Inputs for Binary Counter

What’s next? .. K-maps (4) Minimized Equations for: D0 D1 D2 D3

4-Bit Binary Counter with D Flip-Flops

4-bit Binary Counter Using JK flip-flop

State Table and Flip-Flop Inputs for Binary Counter

K-Maps

Count-Enable Input To control the operation of counter, EN. JQ0 = KQ0 = EN JQ1 = KQ1 = Q0 . EN JQ2 = KQ2 = Q0 . Q1 . EN JQ3 = KQ3 = Q0 . Q1 . Q2 . EN EN = 0; all J and K inputs equal to 0, FFs- no change. EN = 1; JQ0 = KQ0 = 1, and the other equations follow Fig. 5-9.

4-Bit Synchronous Binary Counter

Binary Counter with Parallel Load Counters in digital systems, e.g. computers, often require a parallel-load capability. To transfer an initial binary number into the counter before the count operation. Load = 1; count operation disabled, data transferred from the 4 parallel inputs into the 4 FFs. Load = 0 and Count = 1; normal operation.

4-Bit Binary Counter with Parallel Load

Up-Down Binary Counter

Synchronous Count Down Counter Sequence (reverse): From 1111 to 0000 and back to 1111 to repeat the count. The logic diagram is similar to the count-up counter, except that the inputs to the AND gates must come from the complement outputs of the flip-flops.

Synchronous Up-Down Counter Needs a mode input to select between the two operations. S=1: count up S=0: count down Also need a count enable input, EN: EN=1; normal operation (up/down) EN=0; disable both counts

4-bit BCD Counter Using T flip-flop

State Table and Flip-Flop Inputs for BCD Counter

The scHeMatiC Draw the K-maps and get the minimized equations. .. Draw with four T flip-flops, four AND gates and one Or gate.

Exercise Design a 4-bit Gray Code Counter using D flip-flops

Arbitrary Sequence Counter Using JK flip-flop

Counter with Arbitrary Count

State Table and Flip-Flop Inputs for Counter

Additional BOOK slides

Comparison of 4-bit modulus 16 and modulus 10

Timing diagram Modulus 16

For modulus 10, pay attention at clock 9 , and 10 of modulus 16 At clock 9, Q3..Q0 o/p = 1001 ( in decimal = 9) For modulus 16 At clock 10, Q3..Q0 o/p = 1010 ( in decimal = 10). Here Q3 = 1, Q1 = 1 For modulus 10 Q3 AND Q1 connected by NAND gate. Means when Q1 =1 AND Q3 = 1, o/p of NAND = 0  Happened at clock 10, Q1 = 1 AND Q3 = 1 Q0 Q1 Q2 Q3 Taken from modulus 16 o/p Q1 Q3

Here the o/p of NAND gate will fed into ACTIVE LOW input of CLR. FF0 FF1 FF2 FF3 Here the o/p of NAND gate will fed into ACTIVE LOW input of CLR. Since NAND o/p =0, the Flip-flop will be CLEARED. This introduce glitch in the modulus 10 o/p. Data transmission as described above only happens in a very short time glitch. Data being cleared at clock 10

eXerCisE quEstioNs

Design these Sequential Counters… 3-bit Up-Counter Arbitrary Sequence Counter: 000, 010,011,101,110, 000, ... 3-bit Gray Code Counter

Design these Sequential Counters .. 4-bit Up-Counter Modulus-10 Counter Arbitrary Sequence Counter: 0, 2, 4, 6, 8, 10, 12, 14, 0, … (in decimal)