A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin D. F. Wong Department of Electrical and Computer Engineering University.

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Presentation transcript:

A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin D. F. Wong Department of Electrical and Computer Engineering University of Illinois at Urbana Champaign

Outline  Introduction  Background  Algorithm  Result  Conclusion

Introduction FPGA(Field-programmable gate arrays)  Flexibility and low time-to-market  Consumption cost  A barrier to FPGA use in power-sensitive applications. (mobile devices)

Background  FPGA Architecture

Background  Static power : current leakage in transistors  Dynamic power : signal transitions between logic-0 and logic-1 Functional transitions - necessary for the correct operation of the circuit Glitch - unbalanced delays to the inputs of a logic gate (effect on power consumption)

Background  Dynamic power n : the number of nets in the circuit Si : the switching activity of net I Ci : the capacitance of net I f : the frequency of the circuit Vdd : the supply voltage

Background  Glitch

Background  Routing resource graph  Vr: the input and output pins of logic blocks, and the wire segments.  Er: the feasible connections between the nodes.

Algorithm Overview  To lengthen the short-delay paths to the same delay of the long-delay path  To avoid congestion problem and to ensure that all nets are routed, our algorithm rips-up and re-routes one source-sink pair before balancing the next pair Two issues:  How to select which pairs to be balanced  In what order these selected pairs are to be balanced

Algorithm-Selection criteria  lengthening pathes leads to increased power consumption  Should not try to balance every LUT inputs, but focus on some selected inputs - select the inputs to the first level clusters

Algorithm-Ordering criteria  LUT Input Weighting: some inputs of a LUT have smaller influence on the LUT output than the other inputs, they are less likely to generate glitches

Algorithm-Ordering criteria  Balancing Overhead: - Paths that need more increased delays to be balanced generally introduced more dynamic power overhead - And potentially use more wiring segments, which may prevent other paths to be balanced  Path Ranking:

Algorithm-PathFinding  Input: an FPGA routing-resource graph Gr = (Vr,Er ), with delay information for each node  For a source node s and a sink node t, -To find an (s, t) path such that the delay of the path falls within a specified target (d ± Δ ) -Glitch filtering is handled by setting proper Δ

Algorithm-PathFinding  To keep the runtime under control, we can not try every possible path, but need to have some effective heuristic to limit the search space  One possible approach is to only consider paths that are the combinations of two shortest paths  The shortest path from s to u and the shortest path from u to t may overlap -Two disjoint sets

Algorithm-PathFinding  S: the set of nodes s’ such that d (s, s’) < d (s’, t)  T: the set of nodes t’ such that d (s, t’) ≥ d (t’, t)

Algorithm-PathFinding

Algorithm

Result

Conclusion  This CAD-only approach does not require changes to existing FPGA architectures, and it also does not affect critical-path delay.  An efficient pathfinding algorithm that can find such balancing paths in the routing resource graph.  The GlitchReroute show that on average, 9.8% of dynamic power is reduced.