Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience.

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Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience.

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Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003 Chapter 9: Microprocessor Examples

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic2 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic3 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic4 Source: Microprocessor Report Journal Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14 22/24 Transistors 7.5M24M42M Cache (I/D/L2) 16k/16K/-16K/16K/256K12K/8K/256K Die Size 203mm 2 106mm 2 217mm 2 IC Process 0.28  m, 4M0.18  m, 6M Max Power 27W23W67W Intel® Microprocessor Features

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic5 Clock distribution network with deskewing circuit (Geannopoulos and Dai 1998), Copyright © 1998 IEEE IA-32 Pentium® Pro

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic6 Delay shift register (Geannopoulos and Dai 1998), Copyright © 1998 IEEE IA-32 Pentium® Pro

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic7 Phase detector (Geannopoulos and Dai 1998), Copyright © 1998 IEEE IA-32 Pentium® Pro

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic8 Clock distribution topology (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic9 Deskew buffer architecture (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic10 Digitally controlled delay line (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic11 Simulated regional clock-grid skew (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic12 Measured regional clock skew (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic13 Core and I/O clock generation (Kurd et al. 2001), Copyright © 2001 IEEE Pentium® 4

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic14 Logical diagram of core clock distribution (Kurd et al. 2001), Copyright © 2001 IEEE Pentium® 4

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic15 Example of local clock buffers generating various frequency, phase and types of clocks (Kurd et al. 2001), Copyright © 2001 IEEE Pentium® 4

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic16 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic17 UltraSPARC-I®UltraSPARC-II®UltraSPARC-III® Year ArchitectureSPARC V9, 4-issue Die size17.7x17.8mm x12.5mm 2 15x15.5mm 2 # of transistors5.2M5.4M23M Clock Frequency167MHz330MHz1GHz Supply voltage3.3V2.5V1.6V Process 0.5  m CMOS0.35  m CMOS0.15  m CMOS Metal layers4 (Al)5 (Al)7 (Al) Power consumption <30W <80W UltraSPARC® Family Characteristics

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic18 Clock distribution delay in UltraSPARC-III (Heald et al. 2000), Copyright © 2000 IEEE UltraSPARC-III®: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic19 Semidynamic flip-flop (Klass 1998), Copyright © 1998 IEEE UltraSPARC-III: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic20 (a)Logic embedding in a semidynamic flip-flop; (b)Two-input XOR function. (Klass, 1998), Copyright © 1998 IEEE UltraSPARC-III: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic21 Dynamic versions of semidynamic flip-flop: single-ended; Differential. (Klass 1998), Copyright © 1998 IEEE UltraSPARC-III: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic22 UltraSPARC-III flip-flop (Heald et al. 2000), Copyright © 2000 IEEE UltraSPARC-III: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic23 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic # transistors [M] Die Size [mm 2 ] 16.8x x x x18.8 Process 0.75  m0.5  m0.35  m0.18  m Supply [V] Power [W] Clk Freq. [MHz] Gates/Cycle Alpha® Microprocessor Features

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic25 Alpha microprocessor final clock driver location: (a) 21064, (b) 21164, (c) (a)(b)(c) Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic clock hierarchy (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic major clock domains (Xanthopoulos et al. 2001), Copyright © 2001 Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic , NCLK clock skew (Xanthopoulos et al. 2001), Copyright © 2001 IEEE Alpha® Microprocessors: Clocking

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic modified TSPC latches (Gronowski et al. 1998), Copyright © 1998 Alpha® µ P: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic : (a) phase-A latch, (b) phase-B latch (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b) Alpha® µ P: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic34 Embedding of logic into a latch: (a) TSPC latch, one level of logic; (b) latch, two levels of logic. (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b) Alpha® µ P: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic flip-flop (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® µ P: Clock Storage Elements

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic36 Critical-path and race analysis for clock buffering and conditioning (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Timing

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic37 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic38 Eichelberger 1983 Hazard-Free Level-Sensitive Polarity-Hold Latch

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic39 General LSSD Configuration

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic40 LSSD Shift Register Latch

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic41 LSSD Double Latch Design

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic42 LSSD SRL with multiplexer used in the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic43 Static multiplexer version of the SRL used in the IBM S/390 G4 (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic44 A clocked storage element is used in the non-timing-critical timing macros of the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic45 The clock-generation element used to detect problems created with fast paths: IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic46 The experimental IBM PowerPC processor (Silberman et al. 1998), reproduced by permission IBM® PowerPC Processor

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic47 The PowerPC 603 MSL (Gerosa et al. 1994), Copyright © 1994 IEEE IBM® PowerPC 603: Master-Slave Latch

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic48 The PowerPC 603 local clock regenerator (Gerosa et al. 1994), Copyright © 1994 IEEE IBM® PowerPC 603: Local Clk Generator

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic49 Summary Intel® Microprocessors Active clock deskewing in Pentium® processors Sun Microsystems® Processors Semidynamic flip-flop (one of the fastest single-ended flip-flops today, “soft-edge”) Alpha® Processors Performance leader in the ‘90s Incorporating logic into CSEs IBM® Processors Design for testability techniques Low-power champion PowerPC 603