2. Chapter 11 Timing Issues in Digital Systems Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory August 20, 2004; Revised - July 5, 2005

3. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 2 Goals of This Chapter  Introduction to timing issues in digital design  Classification of Digital systems  Impact on performance and functionality  Clock Skew  Clock Jitter  Clock-Distribution Techniques

4. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 3 Timing Classifications  Synchronous systems  All memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal (i.e., a global clock signal)  Functionality is ensure by strict constraints on the clock signal generation and distribution to minimize  Clock skew  Clock skew (spatial variations in clock edges)  Clock jitter  Clock jitter (temporal variations in clock edges)

5. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 4 Timing Classifications II  Asynchronous systems  Self-timed (controlled) systems  No need for a globally distributed clock, but have asynchronous circuit overheads (handshaking logic, etc.)  Hybrid systems  Mesochronous and Plesiochronous Systems  Synchronization  Synchronization between different clock domains  Interfacing between asynchronous and synchronous domains

6. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 5 Synchronous System Timing Basics t clk1 = t clk2  Under ideal conditions (i.e., when t clk1 = t clk2 ) T  t c-q + t plogic + t su t hold ≤ t cdlogic + t cdreg t c-q, t su, t hold, t cdreg clk t clk1 t clk2 D QR1CombinationalLogic D QR2In t c-q, t su, t hold, t cdreg Maximum Clock Period, T t plogic, t cdlogic

7. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 6 Clock Uncertainties PLL 1 clock generation 2 clock drivers 4 power supply 3interconnect 6 capacitive load 7 capacitive coupling 5temperature spatial temporal  Under real conditions, clock signal can have both spatial and temporal variations  Systematic (Deterministic)  Systematic (Deterministic) - easy to model and correct for at design time  Random  Random - difficult to model and eliminate

8. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 7 Clock Nonidealities t SK Pink + Orange  Clock skew, t SK (Pink + Orange)  Spatial variation in temporally equivalent clock edges  Can be either deterministic or random or both BlueOrange  Clock jitter (Blue + Orange)  Temporal variations in consecutive edges of the clock signal  Modulation and random additive noise t JS t JL  Short term (cycle-to-cycle) t JS and long term t JL  Variation of the pulse width  Important for level sensitive clocking

9. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 8Clk Clk t SK t JS Clock Skew and Jitter  Both clock skew and jitter affect the effective cycle time  Only clock skew affects the race margin

10. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 9 Distribution of Clock Skew Earliest occurrence of Clk edge Nominal –  /2 # of registers Clk delay Insertion delay Latest occurrence of Clk edge Nominal +  /2 Max Clk skew  NegativePositive

11. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 10 Positive Clock Skew clk t clk1 t clk2 delay T  > 0 > 0 > 0 > 0  + t hold T +   t c-q + t plogic + t su T  t c-q + t plogic + t su -  T +   t c-q + t plogic + t su so T  t c-q + t plogic + t su -  t hold +  ≤ t cdlogic + t cdreg t hold ≤ t cdlogic + t cdreg -  t hold +  ≤ t cdlogic + t cdreg so t hold ≤ t cdlogic + t cdreg -   Clock and data flow in the same direction D QR1CombinationalLogic D QR2In T +  1 2 3 4

12. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 11 Negative Clock Skew D QR1CombinationalLogic D QR2In clk t clk1 t clk2 delay T  < 0 < 0 < 0 < 0 T +   t c-q + t plogic + t su T  t c-q + t plogic + t su -  T +   t c-q + t plogic + t su so T  t c-q + t plogic + t su -  t hold +  ≤ t cdlogic + t cdreg t hold ≤ t cdlogic + t cdreg -  t hold +  ≤ t cdlogic + t cdreg so t hold ≤ t cdlogic + t cdreg -  2 13 4 T +   Clock and data flow in opposite direction

13. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 12 T - 2t jitter  t c-q + t plogic + t su so T  t c-q + t plogic + t su + 2t jitter Jitter directly reduces the performance of a sequential circuit Clock Jitter T  Jitter causes T to vary on a cycle-by-cycle basis clk t clk D QR1CombinationalLogic In T -t jitter +t jitter

14. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 13 t clk1 t clk2  > 0 -t jitter T  t c-q + t plogic + t su -  + 2t jitter t hold ≤ t cdlogic + t cdreg –  – 2t jitter Combined Impact of Skew and Jitter  Constraints on the minimum clock period (  > 0) D QR1CombinationalLogic D QR2In 1 612 T T + 

15. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 14 Note on Clock Skew  For Positive Clock skew improves t hold t hold  For Positive Clock skew:  > 0 improves performance, but makes t hold harder to meet. If t hold is not met (race conditions), the circuit malfunctions independent of the clock period!  For Negative Clock skewdegrades t hold  For Negative Clock skew:  < 0 degrades performance, but t hold is easier to meet (eliminating race conditions)  For Skew with Jitter t hold harder  For Skew with Jitter:  > 0 with jitter degrades performance, and makes t hold even harder to meet. (The acceptable skew is reduced by jitter.)

16. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 15 Clock Distribution Networks  Clock skew and jitter can ultimately limit the performance of a digital system, so designing a clock network that minimizes both is important  In many high-speed processors, a majority of the dynamic power is dissipated in the clock network.  To reduce dynamic power, the clock network must support clock gating (shutting down (disabling the clock) units)

17. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 16 Clock Distribution Factors  Things to consider  Interconnect material used for routing clock  Shape of network  Clock drivers and buffers used  Load on clock lines  Rise and fall time of clock (may have to consider transmission line effects as well!!)  Skew specifications

18. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 17 Clock Distribution Techniques H-treematched RC  Balanced paths (H-tree network, matched RC trees)  In the ideal case, can eliminate skew  Could take multiple cycles for the clock signal to propagate to the leaves of the tree  Clock grids  Typically used in the final stage of the clock distribution network  Minimizes absolute delay (not relative delay)

19. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 18 Clock Clock Idle condition Gated clock Insert clock gating at multiple levels in clock tree Shut off entire subtree if all gating conditions are satisfied perfectly  If the paths are perfectly balanced, clock skew is zero H-Tree Clock Network

20. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 19 DEC Alpha 21164 (EV5)  300 MHz clock (9.3 million transistors on a 16.5x18.1 mm die in 0.5 micron CMOS technology)  single phase clock  3.75 nF total clock load  Extensive use of dynamic logic  20 W (out of 50W) or 40% in clock distribution network  Two level clock distribution  Single 6 stage driver at the center of the chip  Secondary buffers drive the left and right sides of the clock grid in m3 and m4  Total equivalent driver size of 58 cm !!

21. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 20 DEC Alpha 21164

22. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 21 Clock Skew in Alpha Processor  Absolute skew smaller than 90 ps The critical instruction and execution units all see the clock within 65 ps

23. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 22 Dealing with Clock Skew and Jitter H-tree matched-tree  To minimize skew, balance clock paths using H-tree or matched-tree clock distribution structures.  If possible, route data and clock in opposite directions  Eliminates races at the cost of performance.  The use of gated clocks to help with dynamic power consumption make jitter worse.  Shield clock wires (route power lines – VDD or GND – next to clock lines) to minimize/eliminate coupling with neighboring signal nets.

24. B.Supmonchai 2102-545 Digital ICs Timing Issues in Digital Systems 23 Dealing with Clock Skew and Jitter II  Use dummy fills to reduce skew by reducing variations in interconnect capacitances due to interlayer dielectric thickness variations. Power supply noise fundamentally limits the performance of clock networks.  Beware of temperature and supply rail variations and their effects on skew and jitter. Power supply noise fundamentally limits the performance of clock networks.