ECE4430 Project Presentation OPERATIONAL AMPLIFIER GROUP3 – DEBASHIS BANERJEE JASON PINTO ASHITA MATHEW

DESIGN SPECIFICATIONS Technology Node – TSMC 0.18µm Required Design Specifications Technology node TSMC 0.18µm Supply (V) 2 Max Power consumption (uW) 150 Differential Gain (dB) 100 CMRR (dB) ICMR (V) 0 - 2.5 Output Swing (V) 0 - 2 Bandwidth - 3dB (kHz) 10 Loading (pF || kOhm) 10 || 100 Slew Rate (V/us) 20 ECE 4430 Project2 Presentation 4/24/2017

BMR & BIASING CIRCUIT ECE 4430 Project2 Presentation 4/24/2017

OPERATIONAL AMPLIFIER -TOPOLOGY USED ECE 4430 Project2 Presentation 4/24/2017

Transconductance stabilization circuit Literature reference : M.M. Ahmadi, R. Lotfi, M. Sharif-Bakhtiar, “A New Architecture for Rail-to-Rail Input Constant-gm, CMOS OperationaI Transconductance Amplifiers ” , ISLPED ‘03 ECE 4430 Project2 Presentation 4/24/2017

INITIAL DESIGN STEPS Redesigned BMR with 5uA reference current Designed short channel biasing circuit Total current budget = 75uA for a max power consumption of 150uW The transconductances of the PMOS NMOS pair of amplifying devices were made equal by sizing the PMOS to NMOS in the ratio kpn:kpp (5:1) Current combining stage is made low voltage headroom cascode with floating current sources for proper biasing. The transconductance stage of diffamp was biased with 5uA each and the summing stage was designed for a current of 30uA For a rail to rail output swing, we designed a class AB push pull amplifier Using CC= 0.22CL caused the bandwidth to be about 100Hz only. Compensation capacitor was fine tuned iteratively to achieve a desired phase margin and maximum bandwidth possible. ECE 4430 Project2 Presentation 4/24/2017

MAGNITUDE- PHASE PLOT ECE 4430 Project2 Presentation 4/24/2017

ICMR : - 0.4 V to 2.23V PHASE MARGIN OVER vcm 90.32dB, 2.23V 90.32dB, -0.41V 56 degrees 50.09 degrees ECE 4430 Project2 Presentation 4/24/2017

OUTPUT VOLTAGE SWING : 0 - 2V -0.25 V , 93dB 2.25V, 88dB 90.32dB, -0.41V 90.32dB, 2.23V ECE 4430 Project2 Presentation 4/24/2017

No ringing observed in output waveform. Settling time =0 SLEW RATE Rise time = 175 ns Fall time = 171ns No ringing observed in output waveform. Settling time =0 Positive slew rate = 9.224 V/us Negative slew rate = -9.275 V/us ECE 4430 Project2 Presentation 4/24/2017

MINIMUM AND MAXIMUM SUPPLY VOLTAGE ECE 4430 Project2 Presentation 4/24/2017

CMRR ACHIEVED = 140dB ECE 4430 Project2 Presentation 4/24/2017

PSRR FOR VDD MEASUREMENT OF PSRR PSRR FOR GND 108.8 dB PSRR FOR GND 108.8 dB ECE 4430 Project2 Presentation 4/24/2017

INPUT REFERRED NOISE ECE 4430 Project2 Presentation 4/24/2017 35.57nV/sqrt(Hz) ECE 4430 Project2 Presentation 4/24/2017

GAIN BANDWIDTHS Loaded GBW = 17.36 MHz Unloaded GBW = 18.04 MHz Unloaded BW = 434 Hz Loaded GBW = 17.36 MHz Unloaded GBW = 18.04 MHz ECE 4430 Project2 Presentation 4/24/2017

MEASUREMENT OF INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE = -2.01uV MEASUREMENT OF INPUT OFFSET VOLTAGE NOMINAL OUTPUT VOLTAGE = 0.8 V ECE 4430 Project2 Presentation 4/24/2017

POWER CONSUMPTION CURVES without load with load ECE 4430 Project2 Presentation 4/24/2017

Op-Amp Final Specs and Simulation Results: PARAMETER SPECS ACHEIVED 1 Differential amplifier topology  Folded cascode with modifications 2 Reference topology  Drain regulated BMR 3 Minumum Supply Voltage (V)   1.66 V 4 Maximum Supply Voltage (V) 2.84V 5 Gain of differential amplifier (dB)   95dB 6 CMRR (dB)   140dB 7 Reference power consumption (uW)   162 uW 8 OpAmp power consumption with zero input (uW)   144uW 9 OpAmp power consumption with no load (uW)   135uW 10 Total power consumption (uW)   307.1uW 11 Positive Slew Rate (V/us)   9.224V/us 12 Negative Slew Rate (V/us)   -9.275V/us 13 ICMR (Vmin ~ Vmax)   -0.4V – 2.23V 14 Output Swing (Vmin ~ Vmax)   0-2V 15 VDD PSRR (dB)   108.8dB 16 GND PSRR (dB)  108.8dB 17 Nominal output voltage (V)   0.8V 18 Input offset voltage (mV)   0.002mV 19 Unloaded Bandwidth (kHz)   0.434 KHz 20 Loaded Bandwidth (kHz)   0.374KHz 21 Gain bandwidth product (MHz)   17.36MHz 22 Compensation capacitor (pF)   500pF 23 Phase margin (degrees)   58.5 deg 24 Rise time (ns)   175ns 25 Fall time (ns)   171ns 26 Settling time (ns)  0 Input referred noise (V/Hz^0.5)   35.57 nV/sqrt(Hz) ECE 4430 Project2 Presentation 4/24/2017

Required Specifications Specifications acheived DEVIATION FROM SPECS Parameter Required Specifications Specifications acheived Percentage Error 1 Max Power consumption (uW) 150 144 -4% 2 Differential Gain (dB) 100 95 -5% 3 CMRR (dB) 140 +28.5% 4 ICMR (V) 0 - 2.5 -0.4 – 2.23 - 5 Output Swing (V) 0 - 2 0-2 0% 6 Bandwidth - 3dB (kHz) 10 0.374 -96% 7 Slew Rate (V/us) 20 9.22 -53% ECE 4430 Project2 Presentation 4/24/2017

CONCLUSION We observed that increasing the compensation capacitance improves the phase margin at the cost of bandwidth. For our case, the degradation in phase margin did not trade off for an appreciable increase in bandwidth. Better common mode rejection was achieved by cascoding the tail current sources. A gain of 95dB is not significantly deviated from 100dB because the OPAMP operates mainly as a feedback amplifier. Since phase margin is high enough, no ringing is observed for a step response ECE 4430 Project2 Presentation 4/24/2017

Thank you… Questions?? ECE 4430 Project2 Presentation 4/24/2017