ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems

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4 Trends in Applications and Processor Design

5 Trends Driven by Consumer Electronics Time-to-market is king! –Ability to re-target designs to new technology nodes –Ability to turn around ASICs in 3 month cycles Flexible architectures – Allow same semiconductor part to live in multiple design generations Low power designs –System-level and micro-architectural decisions impact power very significantly Software is the queen! –Key differentiation in consumer products is via applications –Early software development is key

6 Move to System-level Design System Level Design Economics Development Cost Time to Revenue Re-spin reduction Productivity Design reuse Platform design Optimization Performance Power / battery life Design updates Complexity Increasing design size HW / SW co-design Verification testbench Design tools to leverage system-level models for RTL design and verification are needed

7 Usage of System Level Model System Level Model Architectural and Performance Analysis SLM to RTL Flows (High Level Synthesis) Functional reference model Faster Simulation Platform for software development

8 Manual Process Imp. SLM RTL Manual Process Algorithmic Micro-architecture User Control Limited ControlBroad Control Process Flow SLM to RTL Gap

9 Power Dilemma Greater power savings opportunities at higher levels of abstraction Greater accuracy of power analysis requires detailed layout information Accurate Switching Activity Accurate Capacitance

10 Status of High-level Modeling Today Majority of design teams still using raw C/C++ –Proprietary modeling of simulation time –Simulation speed and ease of coding are key criteria System-model and RTL partitioning is not consistent –Hard to use system-models for RTL verification System-level modeling and RTL teams do not talk! Several different system models at differing levels of abstraction often exist –Different level of interface/timing accuracy –Different levels of computational accuracy Diverse/non-standard modeling makes the space very fragmented –Very hard to build tools for verification/synthesis

11 SLM to RTL Flows Manual SLM to RTL DESIGN FLOW SLM TO RTL HLS DESIGN FLOW Floating Point Model Fixed Point Model Micro-architecture Definition RTL Design RTL Area/Timing Optimization RTL Synthesis Place & Route Hardware ASIC/FPGA Hardware ASIC/FPGA Place & Route RTL Synthesis Fixed Point C++ Model Floating Point Model High Level Synthesis Constraints Manual Methods Logic Analyzer + + System Level Model Precision RTL or DC ASIC or FPGA Vendor Algorithm Functional Description System Designer Hardware Designer Vendor n Replaces manual RTL creation with automation n Connects system domain to hardware design n Technology based design space exploration. n Up to 20x reduction in RTL creation

12 RTL to layout System Analysis Algorithm GDS2 C/C++ SystemC Design model Target ASIC SLM to RTL Flow High Level Synthesis Technology files (Standard Cells + RAM cuts) RTL Formal Proof (SEC) FPGA synthesis FPGA Netlist FPGA

13 Making ESL/HLM a Reality Standardized levels of abstraction in system-level models –SystemC 2.0 starting to do that Consistency between system-level models and RTL –Coherent system-level and RTL design teams Tool eco-system to link system-level and RTL –System-level model validation –Hardware-software co-simulation –High-level synthesis –Sequential equivalence checking –Sequential/micro-architectural power optimizations at RTL and micro-architectural levels