1. Transaction Level Modeling Definitions and Approximations Trevor Meyerowitz EE290A Presentation May 12, 2005

2. Outline Motivation Recent Definitions  SystemC Definitions  SpecC Definitions  Other Defintions Classifying Models of Microprocessor Microarchitectures

3. Motivating Trends… Moore’s Law (Source: Intel) Greg Spirakis 2003 EMSOFT Keynote  Software is 80% of embedded system development cost  more advanced research needed Increase simulation speed of HLM for architectural exploration and HW/SW codesign Gartner Dataquest forecasts 20% growth in Semiconductor IP Market in 2004 (~$1 Billion) The Design Productivity Gap (Source: 1999 ITRS Roadmap)

4. Motivations for Higher Level Models Architecture Exploration Speed of Development Simulation and Verification Speed Early Software Development Reusability

5. Basic Levels of Abstraction Register Transfer Level Models Logic Gates Layout Algorithmic Models Transaction-Level Models Actual Gates Languages: C/C++, Matlab SystemC, SpecC, Metropolis Verilog, VHDL Communication: Shared Variables Method Calls to Channels Wires and Registers

6. SystemC Definitions Communicating Processes Programmer’s View Cycle-Accurate Models RTL Models Adam Donlin, “Transaction Level Modeling: Flows and Use Models”, CODES’04

7. Concurrent Processes Explicit Concurrency  Easier to handle than extracting from a sequential source  Well suited for hardware modeling Communicating via channels  Point to Point Communication  Method calls instead of signals  Abstracts away the protocols Untimed or Timed DCT FIFO VLD IQNT FIFO

8. Programmer’s View Bus Arb Master CPU Master ASIC Slave Mem Bus Slave Periph. Resembles the architecture  Register Accurate  Useful for SW Development and Prototyping Shared Communication  Potential Arbitration  Blocking vs. Non-blocking Timed or Untimed

9. SpecC Transaction Level Modeling It’s higher than RTL-level, but… Cai and Gajski – define it as:  Explicit Separation of Communication and Computation  Three levels: Untimed, Approximate, Cycle-Accurate  It’s a start, but is still vague We expand upon this in the domain of microprocessors and their use in system level environments Cai, L. and Gajski, D. "Transaction Level Modeling: An Overview," Proceedings of the International Conference on Hardware/Software Codesign & System Synthesis, Newport Beach, CA, October 2003. System Modeling Graph (Copyright  2003 Dan Gajski and Lukai Cai)

10. Other Definitions OCP-TLM Levels of Abstraction Calypto Sequential Equivalence UC Irvine CCATB  Clock Cycle Accurate at Transaction Boundaries Metropolis

11. Levels of Processor Modeling Speed Accuracy Native Execution (Untimed) ISS (Instruction Set Simulator) CAS (Cycle-Accurate Simulator) RTL (Signal Level) What about “approximate” models?

12. Levels of Processor Modeling Speed Accuracy native execution (untimed) ISS (instruction set simulator) CAS (cycle accurate simulator) RTL (signal level) 1x 1/20x 1/100x 1/10000x faster, but still accurate timing annotation

13. The Problem Space Performance Exploration and Estimation of Processor Microarchitectures in System-Level Environment AppS - Application Space – input data and instruction execution trace CompS - Microarchitectural Computation and State CommS - Microarchitectural Communication and State Execution Trace Definition –ExecTrace : AppS  CommS  CompS  AppTrace –AppTrace = { (fetch(i), commit(i), i) |  instructions i  AppS } Means of Exploration –Approximation –Abstraction –Microarchitectural Features Metrics –Quantitative: Speed, Accuracy, Power, etc. –Qualititative: Flexibility, Ease of Use, etc. Communication ComputationApplication

14. Ideal Channels Pipelined Channels Non-Pipelined Channels Pipelined Bus Non-Pipelined Bus Microarchitectural Communication Space Memory Hierarchy Bus/Channels Hierarchy Ideal Memory Caches + Buffers CachesBuffers Non-Ideal Memory (no Caches or Buffers) Performance Cost Communication ComputationApplication

15. Microarchitectural Computation Space Elements –Resources Latencies, Throughput, etc. –Speculation –Buffers Abstractions and Approximations –Instruction Level Models –Simplified Microarchitectural Models Communication ComputationApplication Can Increase or Decrease Performance Based on the Communication System

16. Our Flow Instruction Set Simulator Microarchitecture Model Application Performance Characterization Compiler Instruction Trace Execution Results Produces Timing Numbers Fast & Accurate! Timing Annotated Application Potential Use: (for a given application) 1. Determine a processor’s instruction set 2. Explore the processor’s microarchitecture 3. Annotate performance back to the original application Focus of my Work

17. Final Words Transaction-Level Modeling is an important idea in that it’s higher than RTL, but the term means different things to different people (still…) Many Open Questions Remain  How can the different levels of abstraction be related to one another?  IP interchange standards and methodologies  Can we go from algorithms to rtl and still get good results?

18. References [CCATB] S. Pasricha, N. Dutt, and M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration.”, DAC, June 2004. [OCP] Open Core Protocol Web Site: www.ocpip.orgwww.ocpip.org [SPECC] Cai, L. and Gajski, D. "Transaction Level Modeling: An Overview,“, ISSS-CODES’03. [SYSTEMC] Grotker, T., Liao, S., Martin, G., Swan, S. “System Design with SystemC”, Kluwer Academic, 2002. [SYSC-TLM] Donlin, A. “Transaction Level Modeling: Flows and Use Models”, ISSS-CODES’04