Lecture 4: MIPS Subroutines and x86 Architecture Professor Mike Schulte Computer Architecture ECE 201

MIPS Subroutine Calls When making a subroutine (procedure) call, it is necessary to –Place inputs where they can be accessed by subroutine –Transfer control to subroutine –Peform the desired task –Place the result value(s) where the calling program can access it –Return control to the point of origin –The subroutine caller or callee should save and restore registers used by the subroutine MIPS –Provides instructions to assist in subroutine calls (jal) and returns (jr) –Uses software conventions to » place subroutine input and output values »control which registers are saved/restored by caller and callee –Uses a software stack to save/restore values

Subroutine Calls Stacking of Subroutine Calls & Returns and Environments: A: CALL B CALL C C: RET B: A AB ABC AB A Some machines provide a memory stack as part of the architecture (e.g., VAX) Sometimes stacks are implemented via software convention (e.g., MIPS)

0zero constant 0 1atreserved for assembler 2v0expression evaluation & 3v1function results 4a0arguments 5a1 6a2 7a3 8t0temporary: caller saves...(callee can clobber) 15t7 MIPS: Software conventions for registers 16s0callee saves... 23s7 24t8 temporary (cont’d) 25t9 26k0reserved for OS kernel 27k1 28gpPointer to global area 29spstack pointer 30fpframe pointer 31raReturn Address (HW)

Call-Return Linkage: Stack Frames FP Saved argument registers SP High Mem Low Mem Saved return address Saved saved registers Local arrays and structures

History of the Intel 80x : Intel invents microprocessor : 8080 introduced –8-bit microprocessor –Accumulator machine 1978: 8086 introduced –16 bit microprocessor –Accumulator plus dedicated registers 1980: IBM selects 8088 as basis for IBM PC –8088 is 8-bit external bus version of : 8087 floating point coprocessor –adds 60 floating point instructions –80 bit floating point registers –uses hybrid stack/register scheme

History of the Intel 80x : introduced –24-bit address –memory mapping & protection 1985: introduced –32-bit address –32-bit GP registers 1989: introduced 1992: Pentium introduced 1995: Pentium Pro introduced 1996: Pentium with MMX extensions –57 new instructions –Primarily for multimedia applications 1997: Pentium II (Pentium Pro with MMX)

History of the Intel 80x : Pentium III Introduced Supports Intel’s Internet Streaming SIMD technology –Additional multimedia instructions –Four 32-bit floating point operations in parallel –Average, absolute difference, packed maximum/minimum –Useful in speech recognition, video encoding/decoding 2000: Intanium introduced –Release of IA-64 (RISC-like) architecture –Explicitly Parallel Instruction Computing (EPIC) –128-bit bundle with three instructions and a template –128 general purpose registers and 128 floating point registers –Done by a partnership between HP and Intel –Able to run both UNIX and Microsoft windows Intel architecture was due to the desire for backward compatability –Highly irregular architecture –Over 50 million sold per year

Intel 80x86 Integer Registers

X86 Operand Types x86 instructions typically have two operands, where one operand is both a source and a destination operand. Possible combinations include Source/destination typeSecond source typeRegister RegisterImmediate RegisterMemory MemoryRegister MemoryImmediate No memory-memory or immediate-immediate Immediates can be 8, 16, or 32 bits

80x86 Instructions Data movement (move, push, pop) Arithmetic and logic (logic ops, tests CCs, shifts, integer and decimal arithmetic) Control flow (branches, jumps, calls, returns) String instructions (move and compare) FP data movement (load, load const., store) Arithmetic instructions (add, subtract, multiply, divide, square root, absolute value) Comparisons (can send result to ALU) Transcendental functions (sin, cos, log, etc.)

Top 10 80x86 Instructions °RankinstructionInteger Average Percent total executed 1load22% 2conditional branch20% 3compare16% 4store12% 5add8% 6and6% 7sub5% 8move register-register4% 9call1% 10return1% Total96% ° Simple instructions dominate instruction frequency - support these.

Addressing modes The x86 offers several different addressing modes for accessing memory Register indirectAddress in register (mem[R1]) Base with displacement (8, 16, or 32-bit displacement) Base plus scaled index (8, 16, or 32-bit displacement) Address in base register plus displacement (mem[R1+100]) Address is Base + 2 scale x Index scale = 0, 1, 2 or 3 Base plus scaled index with displacement (8, 16, or 32-bit displacement) Address is Base + 2 scale x Index + disp. scale = 0, 1, 2 or 3

80x86 Instruction Format Instructions sizes vary from 1 to 17 bytes

80x86 Length Distribution

Performance Comparison Pentium Pro vs. MIPS R10000 Benchmark Pro MIPSMIIPS÷Pro SPECint SPECfp The Pentium Pro and MIPS R1000 have comparable performance on integer computations. The MIPS R10000 has much better performance than the Pentium Pro for floating point computations.

Comparison How would you expect the x86 and MIPS architectures to compare on the following. –CPI on SPEC benchmarks –Ease of design and implementation –Ease of writing assembly language & compilers –Code density –Overall performance What other advantages/disadvantages are there to the two architectures.