1. 1 CSE 45432 SUNY New Paltz Chapter 3 Machine Language Instructions

2. 2 CSE 45432 SUNY New Paltz Generic Examples of Instruction Format Widths Variable: Fixed: Hybrid: … … If code size is most important, use variable length instructions If performance is most important, use fixed length instructions

3. 3 CSE 45432 SUNY New Paltz General Purpose Registers Dominate 1975-1995 all machines use general purpose registers Expect new instruction set architecture to use general purpose register Advantages of registers registers are faster than memory registers are easier for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack registers can hold variables -memory traffic is reduced, so program is sped up (since registers are faster than memory) -code density improves (since register named with fewer bits than memory location)

4. 4 CSE 45432 SUNY New Paltz Addressing Objects: Endianess and Alignment Big Endian: address of most significant IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: address of least significant Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msblsb 3 2 1 0 little endian byte 0 0 1 2 3 big endian byte 0 Alignment: require that objects fall on address that is multiple of their size. 0 1 2 3 Aligned Not Aligned

5. 5 CSE 45432 SUNY New Paltz Top 10 80x86 Instructions RankInstructionInteger Average Percent total executed 1load22% 2conditional branch20% 3compare16% 4store12% 5add8% 6and6% 7sub5% 8move register-register4% 9call1% 10return1% Total96% Simple instructions dominate instruction frequency

6. 6 CSE 45432 SUNY New Paltz Machine Language Instructions: More primitive than higher level languages Very restrictive We’ll be working with the MIPS instruction set architecture –similar to other architectures developed since the 1980's –used by NEC, Nintendo, Silicon Graphics, Sony Design goals: maximize performance and minimize cost, reduce design time

7. 7 CSE 45432 SUNY New Paltz MIPS ISA MIPS assumes 32 CPU registers ($0, …., $31) All arithmetic instructions have 3 operands Operand order is fixed (destination first in assembly instruction) Operand of arithmetic instructions are in registers Simple memory addressing mechanism C code:A = B + C + D; E = F - A; MIPS code:add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 t0, s1, s2, … are symbolic names for registers (translated to the corresponding numbers by the assembler). Compiler

8. 8 CSE 45432 SUNY New Paltz Register Usage Conventions Registers hold 32 bits of data Register zero always has the value zero (even if you try to write it)

9. 9 CSE 45432 SUNY New Paltz Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array A word in MIPS is 32 bits long (4 bytes) "Byte addressing" means that the index points to a byte of memory. 2 32 bytes with byte addresses from 0 to 2 32 -1 2 30 words with byte addresses 0, 4, 8,... 2 32 -4 Words are aligned! (the least 2 significant bits of a word address?)... 0 1 2 3 4 5 6 8 bits of data 0 4 8 12... 32 bits of data

10. 10 CSE 45432 SUNY New Paltz Load and Store Instructions A memory address = content of a register + an immediate constantA memory address = content of a register + an immediate constant C code:A[8] = h + A[8]; MIPS code:lw $t0, 32($s3) // Load word add $t0, $s2, $t0 sw $t0, 32($s3) // Store word The compiler stores the address of the first element of array A in register $s3. It is assumed that the value of h is stored in register $s2. Store word has destination last Remember arithmetic operands are registers, not memory!

11. 11 CSE 45432 SUNY New Paltz Summary so far: MIPS — loading words but addressing bytes — arithmetic on registers only add $s1, $s2, $s3$s1 $s1InstructionMeaning add $s1, $s2, $s3$s1 $s1

12. 12 CSE 45432 SUNY New Paltz Example swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

13. 13 CSE 45432 SUNY New Paltz Decision making instructions –alter the control flow, –i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label // branch if $t0 != $t1 beq $t0, $t1, Label // branch if $t0 = $t1 Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label:.... Control Instructions

14. 14 CSE 45432 SUNY New Paltz MIPS unconditional branch instructions: j label Example: if (i!=j) beq $s4, $s5, Lab1 h=i+j;add $s3, $s4, $s5 else j Lab2 h=i-j;Lab1:sub $s3, $s4, $s5 Lab2:... Control Instructions (Continue)

15. 15 CSE 45432 SUNY New Paltz We have: beq, bne, what about Branch-if-less-than? New instruction: if $s1 < $s2 then $t0 = 1 slt $t0, $s1, $s2 else $t0 = 0 Can use this instruction to build "blt $s1, $s2, Label" — can now build general control structures Note that the assembler needs a register to do this, — there are policy of use conventions for registers Control Instructions (Continue)

16. 16 CSE 45432 SUNY New Paltz Instructions, like registers and words of data, are also 32 bits long R-type instruction format: –Example: add $t0, $s1, $s2 –registers have numbers, $t0=8, $s1=17, $s2=18 00000010001100100100000000100000 op rs rt rdshamtfunct I-type instruction format: –Example: lw $t0, 32($s2) 35 18 9 32 op rs rt 16 bit number Machine Language Source registerDestination register Op-code extension

17. 17 CSE 45432 SUNY New Paltz Overview of MIPS Simple instructions all 32 bits wide Very structured, no unnecessary baggage Only three instruction formats In branch instructions, address is relative to PC (next instruction) bne $t4,$t5,Label==> PC = (PC+4) + Label if $t4 = = $t5 In jump instructions, address is relative to the 4 high order bits of PC –Address boundaries of 256 MB. Pseudo Instructions are assembly instructions that are translated by the assembler into one or more MIPS instructions –Example: MOV $t0, $t1 ==> add $t0, $t1, $0 op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ

18. 18 CSE 45432 SUNY New Paltz MIPS 5 Addressing Modes

19. 19 CSE 45432 SUNY New Paltz Immediate instructions (2nd operand is a constant): addi $29, $29, 4 // Add Immediate slti $8, $18, 10 // Set Less Than Immediate andi $29, $29, 6 // AND Immediate ori $29, $29, 4 // OR Immediate To load a 32 bit constant into a register, load each 16 bit separatel lui $t0, 1010101010101010 //First: "load upper immediate" Then must get the lower order bits right, i.e., ori $t0, $t0, 1010101010101010 // OR immediate Constants 10101010101010100000000000000000 1010101010101010 0000000000000000 filled with zeros OR

20. 20 CSE 45432 SUNY New Paltz To summarize:

21. 21 CSE 45432 SUNY New Paltz We've focused on architectural issues –basics of MIPS assembly language and machine code –we’ll build a processor to execute these instructions. Design alternative: –provide more powerful operations –goal is to reduce number of instructions executed –danger is a slower cycle time and/or a higher CPI Sometimes referred to as “RISC vs. CISC” –virtually all new instruction sets since 1982 have been RISC –VAX: minimize code size, make assembly language easy instructions from 1 to 54 bytes long! We’ll look at PowerPC and 80x86 Alternative Architectures

22. 22 CSE 45432 SUNY New Paltz PowerPC Indexed addressing –example: lw $t1,$a0+$s3 // $t1=Memory[$a0+$s3] –What do we have to do in MIPS? Update addressing –update a register as part of load (for marching through arrays) –example: lwu $t0,4($s3) // $t0=Memory[$s3+4];$s3=$s3+4 –What do we have to do in MIPS? Others: –load multiple/store multiple –a special counter register “bc Loop” decrement counter, if not 0 goto loop

23. 23 CSE 45432 SUNY New Paltz 80x86 1978: The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The 80286 increases address space to 24 bits, +instructions 1985: The 80386 extends to 32 bits, new addressing modes 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: MMX is added “This history illustrates the impact of the “golden handcuffs” of compatibility “adding new features as someone might add clothing to a packed bag” “an architecture that is difficult to explain and impossible to love”

24. 24 CSE 45432 SUNY New Paltz A dominant architecture: 80x86 Complexity: –Instructions from 1 to 17 bytes long –one operand must act as both a source and destination –one operand can come from memory –complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement” Saving grace: –the most frequently used instructions are not too difficult to build –compilers avoid the portions of the architecture that are slow “what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”

25. 25 CSE 45432 SUNY New Paltz Instruction complexity is only one variableInstruction complexity is only one variable –lower instruction count vs. higher CPI / lower clock rate Design Principles:Design Principles: 1Simplicity favors regularity 2Smaller is faster 3Good design demands compromise 4Make the common case fast Instruction set architectureInstruction set architecture –a very important abstraction indeed! Fallacy: Most powerful instructions mean higher performance Repeat Prefix (REP) in 80X86 Fallacy: Write in assembly language to obtain the highest performance Summary

26. 26 CSE 45432 SUNY New Paltz 0zero constant 0 1atreserved for assembler 2v0expression evaluation & 3v1function results 4a0arguments 5a1 6a2 7a3 8t0temporary: caller saves...(callee can clobber) 15t7 MIPS: Software conventions for Registers 16s0callee saves... (caller can clobber) 23s7 24t8 temporary (cont’d) 25t9 26k0reserved for OS kernel 27k1 28gpPointer to global area 29spStack pointer 30fpframe pointer 31raReturn Address (HW) Plus a 3-deep stack of mode bits.