2. 1 Computer Architecture COSC 3430 Lecture 3: Instructions

3. The Instruction Set Architecture instruction set architecture software hardware The interface description separating the software and hardware.

4. Computer’s Internal Clock  Frequency:  Frequency is number of complete waves passing per unit time.  It is measured in Hertz (Hz), the number of cycles per second.  1 KHz = 10 3 Hz.  1 MHz = 10 6 Hz.  Series of electrical pulses with fixed interval between pulses (cycle time)  800 MHZ machine = 800x10 6 cyc/sec = 1.25x10 -9 sec/cyc = 1.25 ns/cyc  Synchronizes all components  Updates state: inputs only change stored values at specific instances  Regulate instruction execution: e.g., 1/clock cycle cycle time time for one full cycle

5. Operations of the Computer Hardware Chapter 2.2

6. Assembly Language Instructions  Language of the machine  More primitive than higher level languages e.g., no sophisticated control flow  Very restrictive e.g., MIPS arithmetic instructions  We’ll be working with the MIPS instruction set architecture  similar to other architectures developed since the 1980's  used by NEC, Nintendo, Silicon Graphics, Sony, … Design goals: maximize performance, minimize cost, reduce design time, minimize memory space (embedded systems), minimize power consumption (mobile systems)

7. RISC - Reduced Instruction Set Computer  RISC philosophy  fixed instruction lengths  load-store instruction sets  limited addressing modes  limited operations  MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq) Alpha, …  Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them

8. MIPS Reference Data

9. MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2  Those operands are contained in the datapath’s register file ( $t0, $s1,$s2 )  Operand order is fixed (destination first)

10. MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2  Those operands are contained in the datapath’s register file ( $t0,$s1,$s2 )  Operand order is fixed (destination first) rd rs rt

11. Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d

12. Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d sub$t0, $s1, $s2 add$s0, $t0, $s3 rd rs rt rd b c rd b-c d

13. Operands of the Computer Hardware Chapter 2 section 2.3

14. MIPS Register File  Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file  Holds thirty-two 32-bit registers  With two read ports and  One write port  Registers are  Faster than main memory  Easier for a compiler to use  Can hold variables so that  code density improves (since register are named with fewer bits than a memory location)  Register addresses are indicated by using $ Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 locations 32 5 5 5

15. 0$zero constant 0 (Hdware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hdware)

16. Registers vs. Memory  Arithmetic instructions operands must be registers, — only thirty-two registers provided  Compiler associates variables with registers  What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output

17. Registers vs. Memory  Arithmetic instructions operands must be registers, — only thirty-two registers provided  Compiler associates variables with registers  What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output

18. Accessing Memory  MIPS has two basic data transfer instructions for accessing memory lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory (assume $s3 holds 24 10 )  The data transfer instruction must specify  where in memory to read from (load) or write to (store) – memory address  where in the register file to write to (load) or read from (store) – register destination (source)  The memory address is formed by summing the constant portion of the instruction and the contents of the second register

19.  Memory is viewed as a large, single-dimension array (usually of bytes), with addresses starting at 0 to 2 32 – 1.  A memory address is an index into the array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data

20.  Memory is viewed as a large, single-dimension array, with an address  A memory address is an index into the array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data 32 2 32  2 30 words

21. MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word Character: ASCII 7 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers: 2's complement Floating Point

22. Byte Addresses  Since 8-bit bytes are so useful, most architectures address individual bytes in memory  Therefore, the memory address of a word must be a multiple of 4 (alignment restriction)  Big Endian: leftmost (MSB) byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA  Little Endian:rightmost (LSB) byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

23. Addressing Objects: Endianess and Alignment  Big Endian: leftmost byte is word address  Little Endian: rightmost byte is word address msblsb little endian big endian Alignment restriction: requires that objects fall on address that is multiple of their size. 0 1 2 3 Aligned Not Aligned

24. Addressing Objects: Endianess and Alignment  Big Endian: leftmost byte is word address  Little Endian:rightmost byte is word address msblsb 3 2 1 0 little endian byte 0 0 1 2 3 big endian byte 0 Alignment restriction: requires that objects fall on address that is multiple of their size. 0 1 2 3 Aligned Not Aligned 0 1 2 3

25. MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory... 0 1 0 0 DataWord Address 0 4 8 12 16 20 24... 1 0 0 0... 0 0 1 0... 0 0 0 1... 1 1 0 0... 0 1 0 1... 0 1 1 0 $s3 holds 8

26. MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory... 0 1 0 0 DataWord Address 0 4 8 12 16 20 24... 1 0 0 0... 0 0 1 0... 0 0 0 1... 1 1 0 0... 0 1 0 1... 0 1 1 0 $s3 holds 8 in location 16... 0001

27. Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0]

28. Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0] lw$t0, 8($s3) sub$t0, $t0, $s2 sw$t0, 32($s3)

29. Compiling with a Variable Array Index  Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i

30. Compiling with a Variable Array Index  Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i add$t1, $t1, $s4#addr of A[i] lw$t0, 0($t1) sub$s2, $t0, $s1

31. MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1

32. Review: MIPS Organization Processor Memory 32 bits 2 30 words read/write addr read data write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers ($zero - $ra) 32 5 5 5 ALU 32 0123 7654 byte address (big Endian)  Arithmetic instructions – to/from the register file  Load/store instructions - to/from memory

33. 0$zero constant 0 (Hdware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Review: Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hdware)

34. Review: Unsigned Binary Representation HexBinaryDecimal 0x000000000…00000 0x000000010…00011 0x000000020…00102 0x000000030…00113 0x000000040…01004 0x000000050…01015 0x000000060…01106 0x000000070…01117 0x000000080…10008 0x000000090…10019 … 0xFFFFFFFC1…1100 0xFFFFFFFD1…1101 0xFFFFFFFE1…1110 0xFFFFFFFF1…1111 2 32 - 1 2 32 - 2 2 32 - 3 2 32 - 4 2 32 - 1 1 1 1... 1 1 1 1 bit 31 30 29... 3 2 1 0 bit position 2 31 2 30 2 29... 2 3 2 2 2 1 2 0 bit weight 1 0 0 0... 0 0 0 0 - 1

35. Review: Signed Binary Representation 2’sc binarydecimal 1000-8 1001-7 1010-6 1011-5 1100-4 1101-3 1110-2 1111 00000 00011 00102 00113 01004 01015 01106 01117 2 3 - 1 = -(2 3 - 1) = -2 3 = 1010 complement all the bits 1011 and add a 1