Robust Low Power VLSI ECE 7502 S2015 Analog and Mixed Signal Test ECE 7502 Class Discussion Christopher Lukas 5 th March 2015

Robust Low Power VLSI Requirements Specification Architecture Logic / Circuits Physical Design Fabrication Manufacturing Test Packaging Test PCB Test System Test PCB Architecture PCB Circuits PCB Physical Design PCB Fabrication Design and Test Development Customer Validate Verify Test

Robust Low Power VLSI Intro to Analog Test  Analog testing has been a challenge  Testability does not come as easily as digital testing  Approach in the past was simple:  Add multiplexers for testability  Decide on parameters to be tested – no need to look into specific faults  Create a procedure for extracting parameters  Interesting note: This idea was novel enough for a CICC paper in

Robust Low Power VLSI Intro to Analog Test 4 [1] “Design For Testability For Mixed Analog/Digital ASICs”

Robust Low Power VLSI Intro to Analog Test 5 [1] “Design For Testability For Mixed Analog/Digital ASICs” Example Test Prodedure:

Robust Low Power VLSI Designing a Fault Model  Simulate the physical causes of faults instead of arbitrary varying performance specs  Simulate multiple types of defects  Spot defects (shorts, opens)  Variation in process parameters  Form a model  Model working circuit  Introduce elements to deform behavior  Verify the fault model  Compare and quantify similarities and differences between model and simulation until model is adequate 6 [2] “FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS”

Robust Low Power VLSI Analog Fault Model Example 7 [2] “FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS” Circuit Fault Model

Robust Low Power VLSI Designing a Test Architecture for Advanced Systems  Testing of analog components in SoCs is much more expensive than testing digital components  Digital circuits can often be tested using existing inputs and outputs with little modification  Analog circuits can be affected by additional transistors connected to the circuit  Analog testers are more expensive than digital testers  Gaining access to analog circuits for test in large systems is a challenge  Components with analog circuits are not always connected to the outside world  Test structures can be built that wrap around the analog circuits, giving needed accessibility to necessary parts of analog circuits  These structures will convert the analog cores into virtual digital cores, which will allow use of digital testers  This allows a unified test methodology that results in a reduction in test application time for the SoC  The impact of these structures must also be analyzed in order to understand area overhead and impact on timing 8

Robust Low Power VLSI Test Infrastructure Design 9  Suggests use of Test Access Mechanism (TAM) to allow digital access to all of the cores  Width is partitioned among a number of fixed- width busses and each core is assigned a bus [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Test Infrastructure Design  Analog circuits are digitized to interface with TAM bus  This allows a unified test access for the entire chip  Test patterns can be stored digitally 10 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Analog Test Wrapper  Accommodates all requirements for an Analog Test Wrapper (ATW)  Needs to include lowest cost data converters that will still provide required frequency and accuracy  Needs to include variable clock control for both high and low bandwidth and frequency tests  Self test mode to ensure proper working wrapper 11 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Wrapper Modes and Data Converters  In normal operation of the circuit, the test wrapper is transparent  The MUX selects the signal line to bypass the wrapper  In test mode, multiple tests can be applied to the core serially in time  Each test may have different frequency and TAM width requirements  Because of this, the wrapper must be reconfigured between tests by the controller block  Analog wrappers should be designed by the system integrator  This is because the integrator can collect the specs from each analog designer and make a wrapper that is compatible with all analog cores 12

Robust Low Power VLSI Tests and Requirements  To use ADC-DAC, frequency of analog circuit must be within Nyquist of the converters  RF generally cannot be tested using this technique  If an analog test contains frequencies between f min and f max, sampling frequency must be at least 2 f max  Test time must also be long enough to cover two full periods of lowest frequency signal (2/f min ) 13

Robust Low Power VLSI Case Study  Wrapped analog core with 8 bit DAC-ADC 14 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores” a)Applied analog test b)Analog response of the core c)Response of analog wrapped core

Robust Low Power VLSI Analog Wrapper Optimization  Overall wrapper area can be reduced by using a single wrapper for multiple cores  One downside is that now the cores must be time multiplexed during testing, so if both cores are tested at the same time, the wrapper can only support half the frequency it did before  Less advantageous for analog cores that are not close to each other due to parasitics 15 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Test Cost Optimization  Objective is to minimize test cost in terms of time and area overhead  ω is weighting factor  C T is time  C A is overhead area  Different ways to access cores verses cost 16 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Results  Comparison of Test Time between analog and digital busses  Normalized test cost including equipment is shown in parenthesis 17 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Results  Test time results using the proposed approach 18 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Results  Test time for different combinations of wrapper sharing  Shows normalized time to test 19 [4] “Test infrastructure design for mixed-signal SOCs with wrapped analog cores”

Robust Low Power VLSI Additional Work  Parallel Loopback circuit used to calculate performance parameters of device under test 20 [5] “Parallel Loopback Test of Mixed-Signal Circuits”

Robust Low Power VLSI Additional Work  Calculations are done by using different paths through the test equipment and DUT  Harmonic distortion  Noise Power  Paper includes test algorithm for multiple DUTs 21 [5] “Parallel Loopback Test of Mixed-Signal Circuits”

Robust Low Power VLSI Questions  How can this be made relevant to testing for low power (single core) systems?  The figures in the paper show 8 core SoCs  What can this wrapper concept be extended to beyond analog cores?  At what point in the design and test process and device lifetime is this useful?  How can this idea be improved upon?  What applications or designs is it not useful or optimal? What applications or designs would it be best suited for? 22

Robust Low Power VLSI Papers 1.Fasang, P.P.; Mullins, D.; Wong, T., "Design for testability for mixed analog/digital ASICs," Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988, vol., no., pp.16.5/1,16.5/4, May Meixner, A.; Maly, W., "FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS," Test Conference, 1991, Proceedings., International, vol., no., pp.564,, Oct Sam Huynh; Jinyan Zhang; Kim, S.; Devarayanadurg, G.; Soma, M., "Efficient test set design for analog and mixed-signal circuits and systems," Test Symposium, (ATS '99) Proceedings. Eighth Asian, vol., no., pp.239,244, Sehgal, A.; Ozev, S.; Chakrabarty, K., "Test infrastructure design for mixed-signal SOCs with wrapped analog cores," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.14, no.3, pp.292,304, March Joonsung Park; Shin, H.; Abraham, J.A., "Parallel Loopback Test of Mixed-Signal Circuits," VLSI Test Symposium, VTS th IEEE, vol., no., pp.309,316, April May

Robust Low Power VLSI Paper Map of Analog Test 24 [1] Design for Testability, 1988 [3] Efficient Test Set Design, 1999 Increase Efficiency [2] Fault Modeling, 1991 [4] Test Infrastructure Design, 2006 [5] Parallel Loopback Test, 2008 Increase Complexity Decrease testing time