EECS 318 CAD Computer Aided Design LECTURE 1: Introduction.

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Presentation transcript:

EECS 318 CAD Computer Aided Design LECTURE 1: Introduction

CAD Design approaches Goal of each CAD design flow methodology is to increase productivity of the design engineer Increasing the abstraction level of the design methodology and tools is one approach:

SoC: System on a Chip The 2001 prediction: SoC’s will be > 12M gates How do you create million gate ASICs with same amount of resources?...while Decrease development time Increase functionality and performance Keep small design teams Design Methodology (Design flow) Tools that support the Methodology IP reuse (Intellectual Property)

ASIC and SoC Design flow

Nand gate: behaviorial, transistor, layout Boolean Equation Mask Transistor O <= NOT ( A1 AND B1);

Adder: behavior, netlist, transistor, layout Behavioral model Structural model

Review To appreciate why we need high level design techniques We need to look over the past 30 years of chip development and their growing complexity

Ref:

Memory Technology: DRAM Evolution

SoC: Intel Microprocessor History: Intel 4004, 4-bit, 0.74 Mhz, 16 pins, 2250 Transistors Intel publicly introduced the world’s first single chip microprocessor: U. S. Patent #3,821,715. Intel took the integrated circuit one step further, by placing CPU, memory, I/O on a single chip

SoC: Intel Microprocessor History: Intel 8080, 8-bit, 2 Mhz, 40 pins, 4500 Transistors Altair 8800 Computer Bill Gates & Paul Allen write their first Microsoft software product: Basic

SoC: Intel Microrocessor History: Intel 8088, 16-bit internal, 8-bit external, 4.77 Mhz, 40 pins, Transistors IBM PC/XT 0.128M M RAM 0.360Kb, 5.25” Floppy 10M Hard Disk

SoC: Intel Processor History: Penitum Pro 1995 Intel Pentium Pro, 32-bit,200 Mhz internal clock, 66 Mhz external, Superpipelining, 16Kb L1 cache, 256Kb L2 cache, 387 pins, 5.5 Million Transistors

SoC: System on a chip (beyond Processor) The 2001 prediction: SoC’s will be > 12M gates