1. Lecture 1 ECE 291 -- Spring 2000 ECE 291 Spring 2000 Lecture 1: Microprocessor Evolution & Organization Constantine D. Polychronopoulos Professor, ECE Office: 463 CSRL

2. Lecture 1 ECE 291 -- Spring 2000 History of Microprocessors First microprocessor introduced by Fairchild/Intel: 4004 & 4040, 4-bit proc. Next generation was the 8-bit 8008 & 8080, Zilog Z- 80, followed by the 16-bit 8088/8086. 32-bit microprocessors introduced in 1986 by Intel as the 80386 (or 386) with 32-bit datapath and 32-bit mem. address. This was the beginning of the modern microprocessor. Currently: 64-bit, 30M+ trans. ~1GHz, 4+-issue

3. Lecture 1 ECE 291 -- Spring 2000 The New Era with x486 386-like Integer Processor 387 Numeric Co-processor 8Kb Cache 486 Microprocessor - 486 was clocked at 50MHz, 66 MHz with memory at 33MHz - Half of instructions took 2 clocks and half 1 clock (20-25ns) - A later version at 100MHz and an overdrive 486DX4 were introduced in the early 90’s.

4. Lecture 1 ECE 291 -- Spring 2000 Intel Family of Microprocessors

5. Lecture 1 ECE 291 -- Spring 2000 Superscalar & VLIW Processors Datapath1 64Kb Split (I & D) Cache Pentium Pro Microprocessor Datapath2 Datapath3 Datapath1 >512Kb Split (I & D) Cache Merced - 64-bit EPIC Datapath2Datapath3 Datapath4 128 Int. Registers 128 FP Registers 64 Predicate Registers

6. Lecture 1 ECE 291 -- Spring 2000 Organization of a Computer (PC) Memory System Microprocessor Cache Disk Console Tape I/O System System (Memory) Bus PCI (Peripheral Component Interconnect) bus in most of current PCs

7. Lecture 1 ECE 291 -- Spring 2000 BUS Standards PCI: Peripheral Component Interconnect (General memory bus) USB: Universal Serial Bus (Special I/O bus 10-100Mbps) AGP: Advanced Graphics Port (Graphics I/O bus - > 533Mbps) USB & AGP work in conjunction with the PCI bus

8. Lecture 1 ECE 291 -- Spring 2000 Microprocessor Architecture I-cache I-Fetch Decode & Oper. fetch Alignment Execute D-cache (Memory) Commit Instruction Execution I-cache D-cache Branch Prediction Memory Manag.Unit Datapath Control Unit Bus Interf. Unit Registers Modern Microprocessor Architecture

9. Lecture 1 ECE 291 -- Spring 2000 Pipelining I-Fetch Decode & Oper. fetch Execute Memory Write Back I-Fetch Decode & Oper. fetch Execute Memory Write Back I-Fetch Decode & Oper. fetch Execute Memory Write Back Clock 1 Clock 2 Clock 3 NOW: Before: Instruction 1Instruction 2Instruction 3

10. Lecture 1 ECE 291 -- Spring 2000 Processor Registers ALU registers (AX) User (GP) registers Special (user) registers System registers (used by OS) System registers/buffers (used by I/O system)

11. Lecture 1 ECE 291 -- Spring 2000 Memory System Memory system architecture Memory bus Memory Map (memory layout) BIOS & bootstrapping OS kernel I/O drivers & I/O operations