1 Lecture - 2 M.Tech. – Weekend Programme. 2 EDA Tools 1. Design Entry a.View Logic b.Mentor Graphics (Renoir) c.Cadence Design System d.OrCAD e.ALDEC.

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Presentation transcript:

1 Lecture - 2 M.Tech. – Weekend Programme

2 EDA Tools 1. Design Entry a.View Logic b.Mentor Graphics (Renoir) c.Cadence Design System d.OrCAD e.ALDEC (Active HDL) f.SimuCAD (Silos-3)

3 EDA Tools 2.Design Simulation a.Model Technology (Modelsim) b.Synopsy c.Cadence d.SimulCAD (Silos-3) e.Quick turn Design Systems (Power Suite) f.View Logic (VHD Simulator)

4 EDA Tools 3. Logic Synthesis 1. Synopsis a.FPGA Expressway b.FPGA Compiler 2. Synplify (Synplicity) 3. Exempler Logic (Leonardo Spectrum) 4. View Logic (Intelliflow) 5. Cadence Design System 6. Aldec (Active Synthesis)

5 EDA Tools 4. Programmable Logic (Vendors) a.Xilinx – Xilinx Foundation Series b.Altera – MaxPlus II c.Altera – Quartus II Ver. 4.0 d.Lattice – isp Expert Compiler e.Lucent – ORCA Foundary Development f.Actel – FPGA Development System g.Cypress- Warp2 h.Atmel – FPGA Development System i.Quick Logic – Quick works j.Gate Field – ASIC Master

6 Other HDLs 1.ISPS (Instruction Set Processor Specification) -Behavioral Language -Used to design software based on specific hardware -Statement level timing control, but no gate level control

7 2. TI-HDL TI-HDL (Texas Instruction Hardware Description Language) –Created a Texas Instruments –Hierarchical –Models Synchronous and asynchronous circuits –Non-extendable fixed data types

8 3. ZEUS ZEUS - Created at General Electric - Hierarchical - Functional Descriptions - Structural Descriptions - Clock Timing, but no gate delays - No asynchronous circuits

9 4. TEGAS TEGAS (Test Generation And Simulation) –Structural with behavioral extension –Hierarchical –Allows detailed timing specification

10 5. Verilog Verilog –Essentially identical in function in VHDL –Simpler and syntactically different –Gateway Design Automation Co –Early de facto standard for ASIC programming –Open Verilog International Standard –Programming Language Interface to allow connection to non-Verilog code

11 6. ABEL ABEL –Simplified HDL –PLD Language –Dataflow primitives e.g. registers –Can use to Program Xilinx FPGA

12 7. AHPL AHPL (A Hardware Programming Language) –Dataflow language –Implicit Clock –Does not support asynchronous circuits –Fixed data types –Non-hierarchical

13 8. CONLAN CONLAN (CONsensus LANguage) –Family of Language for describing various levels of abstraction –Concurrent –Hierarchical

14 9. ALTERA ALTERA –Created by Altera Corporation –Simplified dialect of HDL (AHDL: Altera HDL)

CDL CDL (Computer Design Language) –Academic Language for teaching digital systems –Dataflow Language –Non-hierarchical –Contains conditional statements

IDL IDL (Interactive Design Language) –Internal IBM Language –Originally for automatic generation of PLA Structures –Generalized to cover other circuits –Concurrent –Hierarchical