1. Slide 1 2. Verilog Elements

2. Slide 2 Why (V)HDL? (VHDL, Verilog etc.), Karen Parnell, Nick Mehta, “Programmable Logic Design Quick Start Handbook”, Xilinx Coorporation, June 2003, module Mult ( input [15:0] A, input [15:0] B, output [31:0] Y ); assign Y = A * B; endmodule

3. Slide 3 Advantages of HDL languages: –Easy to describe combinational circuits –High-level language – easy to be understand by both human and machine –Projects can be easily PARTITIONED and HIERARCHIZED – supports teamwork! –Allows for Design Reuse –Platform independent –Allows different levels of abstractization (what is this?) Abstractization: Hiding details of a project, insignifiant at a specific level. Abstractization level example Behaviour RTL Logic Layout Algorithmic level. Modelling systems and stimulus Machine-independent description: registers, logic, clocking “Gate-Level” netlist Physical level – technology dependent. For ex: 15um HDL – useful for the upper three levels

4. Slide 4 VERILOG – Generalities Verisign Logic (?) by Verisign. Inc. Historically: 1984 Gateway Design Automation Inc, bought then by Cadence Design Systems, inc. First IEEE standard in 1995: IEEE Std. 1364-1995., then in 2001 – IEEE std 1364-2001, then in 2005 - IEEE Standard 1364-2005 Newest language extention: Verilog – AMS (Analog and Mixed Signal, standardized in 2008) What VHDL/Verilog is used for? –To describe DIGITAL Systems and Circuits –To describe a TESTBENCH (used to test those above…) –Verilog is NOT a Programming language !!! –A Programming Language represents: (incomplete definition?) A set of instructions and data, that is passed through a compiler or interpreter The compiler transforms the set of instructions into machine code The machine code is loaded into a MEMORY and executed by a PROCESSING UNIT –VHDL/Verilog do NOT comply with the above description!!! –Exception: A Testbench can be considered as a multi-threading program

5. Slide 5 VERILOG – Generalities For a (BEHAVIORAL) Simulator: –VHDL/Verilog for Digital Circuits: The Instructions (Statements) are EXECUTED in order to SIMULATE the functionality of the circuit –Testbenches are also EXECUTED to create the input signaling and output verification For a Synthesizer: –VHDL/Verilog for Digital Circuits: The statements are TRANSFORMED into digital elements (Logic gates, registers etc) –Testbenches are, by default, IGNORED by synthesizers Therefore we speak about two types of HDL code: VHDL/Verilog for Synthesis VHDL/Verilog for Tetbenches

6. Slide 6 2.a. VHDL/Verilog for Synthesis

7. Slide 7 VHDL/Verilog for Synthesis Generalities: EVERY DIGITAL CIRCUIT –Contains AT LEAST one input signal (port) (*), (**) –Contains AT LEAST one output signal (port) (**) –It may contain internal signals and lower-level components –(*) Assume the circuit contains an internal signal generator, the input can missing. NOT the case of FPGA designs! FPGA devices NEED EXTERNAL CLOCKING –(**) Circuits with no input and circuits with no output will be removed by the synthesizer in the optimization process. –(**) Same if the input ports are not read, or the output port is never written or constant

8. Slide 8 VHDL/Verilog for Synthesis Moreover: EVERY: –Port –Internal Signal –Internal Component –… is IDENTIFIED by a Name (IDENTIFIER) (*) –(*) The OR gate will be probably described as: assign Cout = C1 | C0; The synthesizer will generate an OR gate. Will the OR gate have no name? –Names i.e. IDENTIFIERA ARE IMPORTANT!

9. Slide 9 Verilog Syntax elements CASE SENSITIVE, keywords always written with small letters Comment: // until the end of line /* …Can extend on more than one line */ A statement (instruction) can extend to more than one line! More than one statements can be on the same line!!! Instruction delimiter: ; (Every instruction ends up with; ) Compound instructions: begin – end: neither begin, nor end are ended with ; Same for statements delimiting “the end of something”: endcase, endmodule etc.

10. Slide 10 Verilog Syntax elements List Delimiter :, The last element of a list does not have to be delimited! A list is not ended with, ! In a VHDL/Verilog code we assign signal and/or variable values. Verilog: Two type of assignments: Blocking: ‘=‘ Non-Blocking: for signals: ‘<=‘, for variables: ‘:=‘ Recommendation: In “always” statements use NON- BLOCKING assignments Inside of an “always” statements cannot mix non-blocking and blocking assignments So: use <= for assingmnets

11. Slide 11 Verilog Syntax elements How to give a numerical value to a signal? number_of_bits’[s]number_basevaloare Exemple: 1’b0; 2’b10, 16’hffef, 8’d123; Default numbering base: Decimal What is 0, or 1, or 121? i.e. represented on how many bits? s – signed value i.e. two’s complement Some synthesizers do not support signed value How to treat then a signed value?

12. Slide 12 Verilog Syntax elements USER IDENTIFIERS Can contain letters, numbers, underscore ‘_’, CANNOT contain special characters such as /, ‘, “ MUST start with letters Examples: Mysignal23-- correct rdy, RDY, Rdy-- these are DIFFERENT identifiers vector_/_vector-- NO: Special character, not allowed last line-- Spaces are not allowed next__state -- Two consecutive underscores are NOT allowed 10th_signal-- NO: Starts with a number open, reg -- NO: Are Verilog Keywords

13. Slide 13 Extended Identifiers: The Escape character \ allows for extended identifiers - Verilog ’93 +! \12name – can begin with a number: ALLOWED \last line\ -- ALLOWED \next__state\ -- ALLOWED \open\, \reg\ -- ALLOWED XST: may need extra synthesis options to support Verilog ‘93! Suggestion: try to avoid extended identifiers Verilog Syntax elements

14. Slide 14 Example for Naming convention (Xilinx) -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- parameters: "C_*" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase Verilog Syntax elements