1 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 12: Wed 9/30/2011 (FPGA Features & Convey Computer HC-1) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Mini literary survey due Fri 9/30 midnight (5-10 pages). First exam: next Fri 10/7 in class (take home due following Monday at midnight) –In class portion closed notes Distance students: I’ll send an with how you’ll take this. –Take home, open everything (no interacting with others) Project Teams: Form by Monday 10/10 MP2 due Friday 10/14 Project Advertising/Discussion (Wed 10/5 in class) –Blackboard discussion group to be up this evening –Wed 10/5 in class: I will allocated 5 minutes to each person who would like to present 2-3 slides about their topic to recruit team members. If distances students would like to advertise, then I would be happy to present your slides. Announcements/Reminders

3 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Project Grading Breakdown 50% Final Project Demo 30% Final Project Report –20% of your project report grade will come from your 5-6 project updates. Friday’s midnight 20% Final Project Presentation

4 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA Projects Ideas: Relevant conferences Micro Super Computing HPCA IPDPS

5 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Teams Formed and Topic: Mon 10/10 –Project idea in Power Point 3-5 slides Motivation (why is this interesting, useful) What will be the end result High-level picture of final product –Project team list: Name, Responsibility High-level Plan/Proposal: Fri 10/14 –Power Point 5-10 slides (presentation to class Wed 10/19) System block diagrams High-level algorithms (if any) Concerns –Implementation –Conceptual Related research papers (if any) Projects: Target Timeline

6 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Work on projects: 10/ /9 –Weekly update reports More information on updates will be given Presentations: Finals week –Present / Demo what is done at this point –15-20 minutes (depends on number of projects) Final write up and Software/Hardware turned in: Day of final (TBD) Projects: Target Timeline

7 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) –Team size: 3-4 (5 case-by-case) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

8 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Weekly Project Updates The current state of your project write up –Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section The current state of your Final Presentation –Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation What things are work & not working What roadblocks are you running into

9 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Common Questions

10 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) FPGA Feature and resources Convey Computer HC-1 Overview

11 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) FPGA Features in General LUTs DFFs BlockRAM (on-chip memory) Multipliers CPU processor cores Clock generators and managers Many IP cores: Xilinx provides through Coregen

12 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table ABCD Z B C D A ABCD Z AND Z A B C D ABCD Z OR Z A B C D X000 X001 X010 X101 X110 X111 ABCD Z B 2:1 Mux C D Z 1010

13 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Computational Fabric - DFF 4-LUT Z(t) B C D A DFF Z(t+1) DFF = D Flip Flop

14 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) LUTs and DFF How many and how large is each –Look at Xilinx Virtex-5 family overview 70FX: 330 LXT

15 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) BlockRam: On-chip Memory Embedded Memory bits, 300 MHz

16 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) BlockRam: On-chip Memory Dedicated memory block Embedded Memory Kbits, 550 MHz

17 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) BlockRam: On-chip Memory How many and how large is each –Look at Xilinx Virtex-5 family overview 70FX: 330 LXT

18 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Hard-core 18x18 Multipliers Multiplication Type# LUTsLatencySpeed LUT ~4005 clks380 MHz Dedicated 18x18 Multiplier 03 clks450 MHz Virtex-5 (6-LUTs) 18x18 multiply Very rough estimate of Silicon area comparison (assuming SX95 andLX110 have about the same die size) 6-LUT 18x18 Multiplier In other word you can replace one LUT based 18x18 multiplier With 100 dedicated 18x18 Multipliers!!!

19 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Hard-core multipliers How many and how large is each –Look at Xilinx Virtex-5 family overview 70FX: 330 LXT:

20 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Hard-core or Soft-core Processors Processor PowerPC hard-core MicroBlaze soft-core 500 MHz Super scalor Highspeed 2x5 switch fabric 250 MHz Simple scalar

21 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Hard-core or Soft-core Processor How to use –Xilinx EDK (Embedded Development Kit). –You will use for MP3, and an in class demo of using EDK will be given

22 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Clock Generation: DCM and PLLs Why? –Because you may corrupt packets, causing the OS to drop the packet before your application can see it Tcpdump –Useful program for viewing low level network traffic –Typical need greater than regular user access Example usage –sudo /usr/sbin/tcpdump -i eth0 -v -s 0 -XX

23 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Xilinx IP Cores Xilnx provides may IP core that can be used for your projects Coregen is the tool that is used to configure and create an IP componet. Take a quick look at Coregen –We will do an in class soon after exam 1

24 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Putting the pieces together System on Chip Ethernet MAC DRAM Or SRAM Motor PID Controller Sensor ADC Sensor Data Buffer Dedicated Logic Reconfigurable Logic Matrix Multiplier Coprocessor

25 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Platforms Available The following platforms will be available for doing class projects –ML507 (class’ board), ML506 (DSP apps), ML509 (high logic density) –RAVI Board (Altera-based) –Convey Computer

26 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) ML507

27 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) RAVI Board

28 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Convey HC-1: Highlevel  Socket Filler Module  Bridge FPGA  Implements FSB Protocol  Full Snoop Support  FPGA Based Compute Accelerator  Pre-Defined Vector Instruction Set  Shared Memory Programming Model  ANSI C Support  Accelerator Cache Memory  80 GB/s BW  Snoop Coherent with System Memory  Direct Cache Access CPU FPGA Source: Convey Computer, 2008 Source: Xilinx Corporation, 2009 MC LX155 MC LX155 MC LX155 MC LX155 MC LX155 MC LX155 MC LX155 MC LX155

29 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Next Lecture Exam 1 review & Project Advertising

30 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR

31 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University (Ames) Lecture Notes