18 Bit ADC Status Collaboration meeting May 18, 2007

Early Tests (mostly by Luis) Pedestal Noise good Channels are isolated No apparent crosstalk More later Differential Non-Linearity OK Gave a smooth response to a time varying input

DAC noise works Multiple sampling of base and peak reduce noise Causes other issues Still have negative pedestals A full report will be written

Lead Run We didnt know how to use ADC with timing board Used internal timing but had a mistake

Error: we were integrating over the HV transition Led to a pair ordered asymmetry Problem was resolved but never received low background data.

External timing Working on getting the busy logic right Oversample=0 (one sample per cycle): Integrated value proportional to window

Busy time proportional to sum of ramp delay and window CODA working for oversample=0 and timing board

Oversampling Busy Logic working 256 word readout limit Becomes an issue when doing many oversample and multiple samples Not really a problem because we dont have to flush out ALL data Means we have to assume that ADC is working correctly for this data (which it is for few oversamples) Tested in Stand-alone code, presently incorporating into CODA

Future Prof. Wilson: Separate the regulators between ADC channels, will be done on the next board Ensures no crosstalk Voltage mode Nearly infinite impedance Current mode Works best as current through a resistor

Pedestals The pedestals are negative, but can and will be adjusted Next week will be receiving a prototype board with a resistance pots which will be adjusted on a channel by channel basis so that pedestals are small and positive In Future Pedestals will be adjusted by a DAC Next Board available in August