Download presentation

Presentation is loading. Please wait.

Published byNorman Warren Modified over 6 years ago

1
10/23/2003ME6405 - DAC Lecture1 DAC Sunij Chacko Pierre Emmanuel Deliou Thomas Holst Used with modification

2
10/23/2003ME6405 - DAC Lecture2 Overview What is a DAC? General Characteristics of DACs Types of DACs Binary Weighted Resistor R/2R Ladder Common Errors in DACs Applications

3
10/23/2003ME6405 - DAC Lecture3 Digital to Analog Converter What is a digital to analog converter (DAC)? Converts digital input signal to an analog output signal 01010101 00110011 01110111 10011001 10011001 10101010 10111011 DAC

4
DAC Application

5
10/23/2003ME6405 - DAC Lecture5 Digital to Analog Converter 1011 1001101001111000011001010100 0011001000010000 Digital Input Signal Analog Output Signal

6
10/23/2003ME6405 - DAC Lecture6 What a DAC Looks Like:

7
10/23/2003ME6405 - DAC Lecture7 General DAC Characteristics Resolution Linearity Speed Settling Time Reference Voltages

8
10/23/2003ME6405 - DAC Lecture8 Resolution The variation of the output voltage corresponding to the variation of the least significant binary bit (LSB) Inversely proportional to the number of bits Commonly 12-bit because of tradeoff between cost and resolution

9
10/23/2003ME6405 - DAC Lecture9 Linearity Consistency of step sizes

10
10/23/2003ME6405 - DAC Lecture10 Speed Rate of conversion of a single digital signal to its analog equivalent Depends on: Clock speed of input signal Settling time of DAC

11
10/23/2003ME6405 - DAC Lecture11 Settling Time t settling ½ LSB +-+-

12
10/23/2003ME6405 - DAC Lecture12 Reference Voltages Non multiplier DAC: V ref is fixed—given by the Manufacturer Multiplier DAC: V ref can be variable Multiplies digital word by analog V ref input

13
10/23/2003ME6405 - DAC Lecture13 Full Scale Voltage Full scale voltage is determined using the reference voltage

14
Digital-to-Analog Conversion 2 Basic Approaches Weighted Summing Amplifier R-2R Network Approach

15
Weighted Sum DAC One way to achieve D/A conversion is to use a summing amplifier. This approach is not satisfactory for a large number of bits because it requires too much precision in the summing resistors. This problem is overcome in the R-2R network DAC.

16
10/23/2003ME6405 - DAC Lecture16 Binary Weighted Resistor DAC R/2 n R DAC Variation on the inverting summer op-amp circuit

17
10/23/2003ME6405 - DAC Lecture17 Binary Weighted Resistor DAC Analysis Recall inverting summer Op-Amp: Set the input resistor values at multiple powers of two. Using KCL and Op-Amp properties V (-) = V (+) = 0 V Inverting summer Op-Amp Starting from V1 and going through V3, this would give each input voltage exactly half the effect on the output as the voltage before it.

18
10/23/2003ME6405 - DAC Lecture18 Binary Weighted Resistor DAC Analysis Binary inputs; so that each input is either 0 volts or full supply voltage, the output voltage will be an analog representation of the binary value of these bits. A reference voltage defines the full scale of the converter

19
10/23/2003ME6405 - DAC Lecture19 Binary Weighted Resistor DAC The output will be:

20
10/23/2003ME6405 - DAC Lecture20 Binary Weighted Resistor DAC Example: Full scale voltage:

21
10/23/2003ME6405 - DAC Lecture21 Binary Weighted Resistor DAC Advantage Advantage Easy principle (low bit DACs) Disadvantages Requirement of several different precise input resistor values: one unique value per binary input bit. (High bit DACs) Larger resistors ~ more error. Precise large resistors – expensive. High number of bits lead to current changes in the magnitude of noise amplitudes.

22
Weighted Sum DAC

23
R-2R Ladder DAC

24
10/23/2003ME6405 - DAC Lecture24 R-2R Ladder DAC Network of R and 2R resistances Most commonly used

25
R-2R Ladder DAC

26
The summing amplifier with the R-2R ladder of resistances shown produces the output where the D's take the value 0 or 1. The digital inputs could be TTL voltages which close the switches on a logical 1 and leave it grounded for a logical 0. This is illustrated for 4 bits, but can be extended to any number with just the resistance values R and 2R.

27
10/23/2003ME6405 - DAC Lecture27 R-2R Ladder DAC Analysis Weighting factors using Thevenin Analysis Summing Op-Amp Properties

28
10/23/2003ME6405 - DAC Lecture28 R-2R Ladder DAC Analysis Thevenin Analysis:

29
10/23/2003ME6405 - DAC Lecture29 R-2R Ladder DAC Analysis Thevenin Analysis Example:

30
10/23/2003ME6405 - DAC Lecture30 R-2R Ladder DAC Analysis

31
10/23/2003ME6405 - DAC Lecture31 R-2R Ladder DAC Analysis The output will be:

32
10/23/2003ME6405 - DAC Lecture32 R-2R Ladder DAC Only two resistor values- R and 2R Does not need the kind of precision as Binary weighted DACs Easy to manufacture More popular Less errors

33
DAC0830/DAC0832 8-Bit µP Compatible DAC An advanced CMOS/Si-Cr 8-bit multiplying DAC designed to interface directly with the 8080, 8048, 8085, Z80®, and other popular microprocessors. A deposited silicon-chromium R-2R resistor ladder network divides the reference current and provides the circuit with excellent temperature tracking characteristics (0.05% of Full Scale Range maximum linearity error over temperature).

34
Typical Application

35
10/23/2003ME6405 - DAC Lecture35 Common DAC Errors 3. DAC Errors Gain Error Offset Error Non-Linearities Monotony

36
10/23/2003ME6405 - DAC Lecture36 Gain Error Distance between the theoretical value and the real value measured on the last transition of the converter and expressed in LSB. Assumes the adjustment of the zero is completed.

37
10/23/2003ME6405 - DAC Lecture37 Offset Error Distance between the theoretical value and the real value measured on the first transition of the converter and expressed in LSB

38
10/23/2003ME6405 - DAC Lecture38 Linearity The linearity error of is due to the fact that the resolution of the converter is not constant Two types: Integral non linearity Differential non linearity

39
10/23/2003ME6405 - DAC Lecture39 Integral non-linearity It is the maximum difference noticed on all the range of conversion between the theoretical values and the real values

40
10/23/2003ME6405 - DAC Lecture40 Differential non linearity It is the difference of tension obtained during the passage in the next digital code. Should be 1 LSB in theory.

41
10/23/2003ME6405 - DAC Lecture41 Monotony Inflection in the transfer function For one Output value, two binary input are possible.

42
10/23/2003ME6405 - DAC Lecture42 Overall Precision It’s the sum of all previous errors. It’s given in a percentage of the full scale.

43
10/23/2003ME6405 - DAC Lecture43 Applications Conventional use Programmable gain OpAmps Programmable Filters Multiplier

44
10/23/2003ME6405 - DAC Lecture44 Conventional use Used at the end of a digital processing chain when an analog signal is required. It will be followed by a filter in order to abolish the ‘steps’ inherent to the digitalization.

45
10/23/2003ME6405 - DAC Lecture45 Programmable gain OpAmps Voltage controlled Amplifier (digital input, Vref as control) Digitally operated attenuators (Vref as input, digital control)

46
10/23/2003ME6405 - DAC Lecture46 Programmable Filters Integrate DACs in filters Variable cutoff frequency commended by a digital signal

47
10/23/2003ME6405 - DAC Lecture47 References http://www.allaboutcircuits.com http://www.allaboutcircuits.com http://www.dwelle.de/rtc/infotheque/digital_signal/conversion.pdf http://www.dwelle.de/rtc/infotheque/digital_signal/conversion.pdf http://hyperphysics.phy-astr.gsu.edu http://hyperphysics.phy-astr.gsu.edu http://www.fujitsu.com http://www.fujitsu.com

48
10/23/2003ME6405 - DAC Lecture48 Acknowledgements Dr. I. Charles Ume Teaching Assistants Students from previous years.

49
PIC18 Connection to DAC0808 and Op-Amp Example: Binary input: 10011001 I out = 2mA (153/256) = 1.195mA and V out = 1.195mA x 5K = 5.975V

Similar presentations

© 2021 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google