Shashi Kumar 1 Logic Synthesis: Course Introduction Shashi Kumar Embedded System Group Department of Electronics and Computer Engineering Jönköping Univ.

Slides:



Advertisements
Similar presentations
Digital System Design Subject Name : Digital System Design Course Code : IT-314.
Advertisements

Microcomputer Circuits Prof Jess UEAB 2007 Designing a Microprocessor Chapter 1.
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
ECE Synthesis & Verification - Lecture 2 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits High-Level (Architectural)
Give qualifications of instructors: DAP
ECE 551 Digital System Design & Synthesis Lecture 08 The Synthesis Process Constraints and Design Rules High-Level Synthesis Options.
University Of Vaasa Telecommunications Engineering Automation Seminar Signal Generator By Tibebu Sime 13 th December 2011.
EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 1 Ch3. Combinatorial Logic Design Modern digital design involves a number of techniques and tools essential.
ECE Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Introduction.
Behavioral Synthesis Outline –Synthesis Procedure –Example –Domain-Specific Synthesis –Silicon Compilers –Example Tools Goal –Understand behavioral synthesis.
ELEN 468 Lecture 121 ELEN 468 Advanced Logic Design Lecture 12 Synthesis of Combinational Logic I.
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Spring 08, Jan 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.
Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 3 Microcomputer Systems Design (Embedded Systems)
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.
COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals.
ECE Lecture 1 1 ECE 3561 Advanced Digital Design Department of Electrical and Computer Engineering The Ohio State University.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,
ENEE 644 Dr. Ankur Srivastava Office: 1349 A.V. Williams URL: Computer-Aided Design of.
Digital System Design EEE344 Lecture 1 INTRODUCTION TO THE COURSE
EENG 2910 – Digital Systems Design Fall Course Introduction Class Time: M9:30am-12:20pm Location: B239, B236 and B227 Instructor: Yomi Adamo
Design methodology.
Electronic Design Automation. Course Outline 1.Digital circuit design flow 2.Verilog Hardware Description Language 3.Logic Synthesis –Multilevel logic.
CAD Techniques for IP-Based and System-On-Chip Designs Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {
1 Digital System Design Subject Name : Digital System Design Course Code : IT- 308 Instructor : Amit Prakash Singh Home page :
Principles Of Digital Design Chapter 1 Introduction Design Representation Levels of Abstraction Design Tasks and Design Processes CAD Tools.
CAD for Physical Design of VLSI Circuits
Synthesis Presented by: Ms. Sangeeta L. Mahaddalkar ME(Microelectronics) Sem II Subject: Subject:ASIC Design and FPGA.
PROGRAMMABLE LOGIC DEVICES (PLD)
40551 Logic Synthesis Optimization Dr. Yaser M. Agami Khalifa Fall 2004 Lecture # 1.
TO THE COURSE ON DIGITAL DESIGN FOR INSTRUMENTATION TO THE COURSE ON DIGITAL DESIGN FOR INSTRUMENTATION.
Digital System Design Pradondet Nilagupta Department of Computer Engineering.
CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.
Welcome CSC 480/580 – Digital Logic & Computer Design Term: Winter 2002 Instructor: William T Krieger.
COE 405 Design and Modeling of Digital Systems
Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.
COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals.
IKI10201: Introduction to Digital Systems Bobby Nazief Semester-I The materials on these slides are adopted from those in CS231’s Lecture Notes.
Digital Logic Design and Lab School of EECS Seoul National University.
ECE 3110: Introduction to Digital Systems Introduction (Contd.)
Module 1.2 Introduction to Verilog
Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.
Spring 2007 W. Rhett Davis with minor editing by J. Dean Brock UNCA ECE Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 1: Introduction.
1 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 5: 9/7/2011.
ECE-C662 Lecture 2 Prawat Nagvajara
1 Synthesizing Datapath Circuits for FPGAs With Emphasis on Area Minimization Andy Ye, David Lewis, Jonathan Rose Department of Electrical and Computer.
1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
Teaching Digital Logic courses with Altera Technology
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
1 Overview of CS 151 Fall Combinational Logic Design –Simplifying a logic function using algebraic method –Truth table and logic function representation.
1 Digital Logic Design (41-135) Introduction Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2006.

SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.
EMT 351/4 DIGITAL IC DESIGN Week # 1 EDA & HDL.
Combinational Logic Design
Sequential Networks and Finite State Machines
Introduction Introduction to VHDL Entities Signals Data & Scalar Types
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
ECNG 1014: Digital Electronics Lecture 1: Course Overview
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
Introduction to Micro Controllers & Embedded System Design
VHDL Introduction.
HIGH LEVEL SYNTHESIS.
ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.
Digital Designs – What does it take
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
Presentation transcript:

Shashi Kumar 1 Logic Synthesis: Course Introduction Shashi Kumar Embedded System Group Department of Electronics and Computer Engineering Jönköping Univ.

Shashi Kumar 2 23 rd Oct Outline  Objectives and scope of the course  Course Overview  Laboratory Organization  Literature

Shashi Kumar 3 23 rd Oct Course Objectives  To learn techniques to synthesize digital circuits at logic level.  Specifation of circuits at logic level  Combinational Circuits  Sequential circuits  Optimization of logic circuits  Minimize cost( area)  Delay/ Clock period  Technology Mapping or Library Binding  Implement the logic circuit using a given set of library components  Implement the circuit using FPGAs

Shashi Kumar 4 23 rd Oct Course Scope  You will:  Learn theory used to design logic synthesis tools  Use a Public Domain Logic Synthesis tool called SIS (from Univ. Of California, Berkeley )  Do small digital circuit design in the laboratory and optimize them using SIS.  You will not learn in this course:  Lower level physical design  Higher level behavioral design  A hardware description language like VHDL

Shashi Kumar 5 23 rd Oct Course Pre-requisites  Compulsory  Basic knowledge in digital circuit design  Discrete mathematic concepts  Boolean Algebra  Graph Theory  Useful but not compulsory  Some programming experience  Familiarity with UNIX O.S.

Shashi Kumar 6 23 rd Oct Digital System Design Process Behavioral Design Design Idea RTL Design Logic Design Physical Design Manufacturing Net-list of gates and flip-flops Buses, Registers, ALU’s Hardware Description Language

Shashi Kumar 7 23 rd Oct Y-Chart Behavioral Domain Structural Domain Physical Domain Boards, MCM Transistor Layout Cells, Modules Chips, ASICs Flowcharts, Algorithms Register Transfers Boolean Expressions Transistor Functions Processors, Mem, Buses Registers, ALUs, MuXs,. Gates, Flip-Flops - Transistors

Shashi Kumar 8 23 rd Oct Design Processes Structural Domain Physical Domain Boards, MCM Transistor Layout Cells, Modules Chips, ASICs Flowcharts, Algorithms Register Transfers Boolean Expressions Transistor Functions Processors, Mem, Buses Registers, ALUs, MuXs,. Gates, Flip-Flops - Transistors Synthesis Implementation Behavioral Domain

Shashi Kumar 9 23 rd Oct Levels of Abstraction …… PC = PC + 1; IR = Mem( PC); … A = A + B; …. Adder RAMRAM PCPC AB Control U= A*!B + C V = !A*!C+!B …… && + + Behavioral DomainStructural Domain

Shashi Kumar rd Oct Synthesis Synthesis involves the transformation of system description from behavioral domain to structural domain.  Architectural/Behavioral Synthesis  Algorithmic Description  RTL Design  RTL Design : Design using Registers, Adders, Multiplexors, buses etc.  Logic Synthesis  Boolean functions, Finite State Machine  Logic Design  Logic Design: Design using gates and flip-flops  Physical Synthesis  Switching functions  Transistor switches

Shashi Kumar rd Oct Logic Synthesis  Example Sum = !A*!B*C+!A*B*!C+A*!B*!C+A*B*C Cout = !A*B*C+A*!B*C+A*B*!C+A*B*C S0,0 S1,1 S2,2 S3,3 CLK J1 Q1 K1 J2 Q2 K2 ”1” & & & & + Sum

Shashi Kumar rd Oct Logic Optimization Transform the description to an equivalent description so that the cost of the new description is smaller than the original description. Cout = !A*B*C+A*!B*C+A*B*!C+A*B*C Cout = B*C+A*C+A*B V = A*C+AD+A*E+B*C+B*D+B*E V = (A+B)*(C+D+E) Cost: 4 3-input AND gates and 1 4-input OR gate Cost: 3 2-input AND gates and 1 3-input OR gate Cost: 6 2-input AND gates and 1 6-input OR gate Cost: 1 2-input AND gates and 2 3-input OR gate

Shashi Kumar rd Oct Sequential Logic Synthesis Synthesize the behavior of the system in terms of flip-flops and gates. Generic Implementation of an FSM X: set of inputs; Z: set of outputs; N: Number of states S(t+1) = F( S(t), X) Z(t) = G( S(t), X(t)) Number of bits in SR   Log2 N  Objectives  Minimize size of SR  Implement the functions F and G using minimum number of gates. GF XZSRSR S(t) S(t+1)

Shashi Kumar rd Oct FSM Minimization  Transform the given FSM to another equivalent FSM which has lesser number of states.  Equivalent FSM with minimum number of states  Minimizes the size of the state register  The problem is very hard for large FSMs  Hard Problem  Time required to find an equivalent FSM with minimum number of states grows exponentially with number of states. Time = k1 * 2 N ; Time to minimize FSM with 40 states may take years!

Shashi Kumar rd Oct State-Encoding  State Encoding is the task of assigning binary codes to the states of an FSM.  Number of different possibilities of state encodings = O(3 N ), for an FSM with N states.  The hardware cost and speed depends on the codes given to states  Cost of hardware: cost of state register, cost of implementing functions F and G.  Delay depends on the implementation of function F and G  It is important to select a good encoding for states.  The task is very hard!

Shashi Kumar rd Oct Technology Mapping or Library Binding  Technology mapping step in logic synthesis takes an optimized description of circuit and implements it using a restricted set of components from a library.  ASIC Design : using a technology dependent cell library  FPGA: using the blocks of FPGAs  PCB based implementation: components available in lab. or stock  The task in technology mapping is to get an implementation which meets the desired objectives.  Minimum Cost  Minimum Delay  Meets cost and Delay constraints

Shashi Kumar rd Oct Laboratory Objectives  To Learn:  Representations of circuit at logic level  Learn a Computer Aided design tool for:  Two-Level Logic optimization  Multi-Level Logic Optimization  FSM Minimization  FSM Encoding  Technology Mapping

Shashi Kumar rd Oct SIS Tool  SIS is a Logic Synthesis tool developed at University of California, Berkeley.  SIS is installed in a unix machine in Högskolan  SIS accepts circuits in certain formats  BLIF  KISS  SIS consists of a set of commands and has a text interface.  You will use do all your laboratory exercises

Shashi Kumar rd Oct Laboratory Exercises  Exercise 1: Logic Optimization using SIS  Design and optimization of combinational circuit  4-bit unsigned multiplier design  Design and optimization of sequential circuits  Design of a pattern recognizer  Logic optimization of bench-mark circuits  Exercise 2: Technology mapping using SIS  Use SIS to implement the combinational and the sequential circuit designed in exercise 1 onto an FPGA using SIS.

Shashi Kumar rd Oct Text and Reference Books 1.Giovanni De Micheli, Synthesis and optimization of digital circuits, McGraw-Hill International Editions, Electrical Engineering Series, 1994, ISBN Stephen D. Brown, Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992, ISBN Saeyang Yang, ” Logic Synthesis and Optimization Benchmarks user guide Version 3.0”, Report, Microelectronic Center of North Carolina, Box 12889, Research Triangle Park, NC 27709, USA. 4.Ellen M. Sentovich, et. Al.,” SIS: A System for Sequential Circuit Synthesis”, Lectronic Research Laboratory, Memo. Number UCB/ERL M92/41, Department of Electrical Engineering and Computer Science, May 1992.