Under-Graduate Project Mid-Term Paper Reading Presentation Adviser: Prof. An-Yeu Wu Mentor: 詹承洲 第二組 溫仁揚 溫昌懌

2 A New Approach to Pipeline FFT Processor Shousheng He & Mats Torkelson Department of Applied Electronics, Lund University, S Lund, SWEDEN

3 Outline What is FFT How to solve FFT by hardware Approaches to Pipeline FFT A closer look to Radix- Simulation by C language Future Work Conclusion Reference

4 What is FFT Discrete Fourier Transform is defined as: with complexity Fast Fourier Transform (FFT) is an efficient algorithm which reduced the complexity into

5 What is FFT(cont ’ d) The Cooly-Tukey algorithm by symmetry, Hence, we re-express the size N transform into 2 size N/2 transforms

6 How to Solve FFT by Hardwares Divide & Conquer Butterfly Twiddle Factor

7 W(n) – twiddle factor Radix-22DIFFFT :

8 Approach to Pipeline FFT R2MDC R2SDF R4MDC R4SDF

9 Approach to Pipeline FFT (cont ’ d) R4SDC Radix- Still many other approaches, ex: Radix-, Mixed Radix, Chirp-Z … etc. We focus on this structure today

10 A Closer Look to Radix- x(0)+x(8) [x(0)+x(8)]+[x(4)+(12)] W(n)

11 A Closer Look to Radix- (cont ’ d) A 256-point model of Radix- The size of register is 2 n W2(n)=e {- j*(n15*(k11+2*k12) )} W3(n)= e {-j*4*n3*(k21+2*k22)}

12 First clks, push inputs into register file. A Closer Look to Radix- (cont ’ d) Then start to do the butterfly. From +1 clk to next clks, push inputs into register file Then start to do the butterfly

13 A Closer Look to Radix-2 2 counter

14 Simulation by C language (cont ’ d) Main function (A 64 points model) int main(void) { … … //declare variables, assign inputs for(clk=0;clk<=2*N;clk++) { BF2i ( 5,clk>>5 ); //first BF #5 REGIST(5); //first regs BF2ii( 4,clk>>5,(clk>>4)%2 ); //second BF #4 REGIST(4); //second regs Zr[0][4] = W2 * Zr[0][4] ; //twiddle factor } //end of for //print outputs and make comparison to theoretical value } //end of main Do it 3 times with different parameters

15 Simulation by C language (cont ’ d) void BF2i(char t,bool s) // 4 inputs which are Xr(n), Xi(n), Xr(n+N/2), Xi(n+N/2),clk signal in the fiqure { if (s){ Zr[0][t]= Zr[0][t+1]+regr[t][pow(2,t)-1]; Zi[0][t]= Zi[0][t+1]+regi[t][pow(2,t)-1]; Zr[1][t]= regr[t][pow(2,t)-1]-Zr[0][t+1]; Zi[1][t]= regi[t][pow(2,t)-1]-Zi[0][t+1]; }// the vatue of Zs when s==1 else{ Zr[0][t]=regr[t][pow(2,t)-1]; Zi[0][t]=regi[t][pow(2,t)-1]; Zr[1][t]=Zr[0][t+1]; Zi[1][t]=Zi[0][t+1]; }// the value of Zs when s==0 }// end of BF2i regr[t][2^t-1] regi[t][2^t-1] Zr[0][t+1] Zi[0][t+1] Zr[0][t] Zi[0][t] Zr[1][t] Zi[1][t] BF2i

16 Simulation by C language (cont ’ d) S=0 : S=1 :

17 Simulation by C language (cont ’ d) BF2ii void BF2ii(char t, bool s, bool g) { if(g){ if(s){ Zr[0][t]=regr[t][pow(2,t)-1]+Zr[0][t+1]; Zi[0][t]=regi[t][pow(2,t)-1]+Zi[0][t+1]; Zr[1][t]=regr[t][pow(2,t)-1]-Zr[0][t+1]; Zi[1][t]=regi[t][pow(2,t)-1]-Zi[0][t+1]; } else { … } else{ … } Zr[0][t+1] Zi[0][t+1] Zr[1][t] Zi[1][t] regr[t][2^t-1] regi[t][2^t-1] Zr[0][t] Zi[0][t]

18 Simulation by C language (cont ’ d) g=0: g=1, s=0,1:

19 Simulation by C language (cont ’ d) Register void REGIST(char num) { for (char l=pow(2,num-1); l>=1;l--) { // from MSB to LSB regr[num][l]=regr[num][l-1]; regi[num][l]=regi[num][l-1]; } // end of for loop regr[num][0]=Zr[1][num]; regi[num][0]=Zi[1][num]; }//end of function -1 … 1 0 Zr[1][num] Zi[1][num]

20 Simulation by C language (cont ’ d) Simulation results: 16 points completed 64 points with error

21 Future Work Develop more points Perform it in HDL language, ex: Verilog Final Presentation

22 Conclusion Under how to solve FFT by hardware Develop W(n) to 64 points Construct Radix2 2 ‘s model C simulation with some faults

23 Reference Shousheng He & Torkelson, M., ” A new approach to pipeline FFT processor, ” Proceedings of IPPS ’ 96, April 1996, pp Shousheng He & Torkelson, M., ” Designing Pipeline FFT Processor for OFDM (de)Modulation, ” Signals, Systems, and Electronics ’ Sep-2 Oct 1998,pp 施信毓, ” 95-1 Under-Graduate Project, Final Project: single-path Delay Feedback FFT ”,04 Oct ms.htm ms.htm