1. CORDIC Based 64-Point Radix-2 FFT Processor
Inho Cho , Sung-Chul Lim
Information and Communication Engineering,
INHA University
Let My
Project
ICE , Inha University

2. Theme And Core Content Theme Core Content
64-Points Radix-2 CORDIC Based FFT Processor
Core Content
try to apply CORDIC algorithm to FFT processor for improvement
Power consumption, Speed
Problem
Speed, Power consumption
Multiplexer
Out proj
In existing
This
CORDIC As
CORDIC
< FFT Basic Unit >
Project
ICE , Inha University

3. Research Related Paper
Schedule of Project
March
April
May
June 1 2 3 4 5
Choose Theme
& Submit Proposal
Research Related Paper
& C-Coding
Verilog-Coding
FPGA Implementation
Final Presentation
& Make Paper
Contents
Coding
32-bits CORDIC
64-Points 32-bits FFT
64-Points 32-bits FFT based CORDIC
C – Language / SW
Verilog - RTL / HW
We did
From then
Project
ICE , Inha University

4. Jop Distribution & Used Tool
Name
Distribution
조인호
C - 64-point FFT
Research Theory
Make Presentation
Make paper
Verilog - CORDIC, FFT based CORDIC, FPGA
Timing Analysis, Delay, Control module
Coregen, FPGA Implementation
임성철
C – 16-point FFT
Timing Analysis, Butterfly module
FPGA Result Verification
Visual Studio 2008 professional (Software design & implementation)
Xilinx ISE Design Suite 12.3 System Pack (Hardware design & implementation)
FPGA Board : Virtex4 - XCVLX60 - FF668 (Hardware implementation)
We did
From then
Project
ICE , Inha University

5. CORDIC Algorithm FFT Algorithm CORDIC Based FFT 1. 2. 3.
Applied Technology 1.
CORDIC Algorithm 2.
FFT Algorithm 3.
CORDIC Based FFT
CORDIC 5
Project
ICE , Inha University

6. Applied Technology - CORDIC Algorithm
In the vector rotation, it is expressed as follows.
Xj+1 = Xj cosθ - Yj sjnθ (θ=tan-1(2-(j-2))
Yj+1 = Xj sjnθ + Yj cosθ
Xj+1 = cosθ(Xj - Yj tanθ)
Yj+1 = cosθ(Xj + Yj tanθ)
Xj+1 = (Xj - Yj σj2-(j-2))
Yj+1 = (Xj + Yj σj2-(j-2))
Zj+1 = Zj - σjtan-1(2-(j-2)) J 1 2 3 … θ 45
26.5 13
CORDIC
σj = 1 (Zj > 0)
σj = 1 (Zj < 0) 6
Project
ICE , Inha University

7. Applied Technology - CORDIC Algorithm
CORDIC Algorithm Example / Find sin(65˚), cos(65˚)
Setting
Step1
Step2
Step3
CORDIC
Z16 = 0 (convergenced to zero)
X16 = COS(65 ˚)
Y16 = SIN(65 ˚)
Continue up to Step16 7
Project
ICE , Inha University

8. Applied Technology - CORDIC Algorithm
CORDIC Algorithm Diagram
16 operation is configured as pipeline R
65 ˚
(65)
16 rotations
CORDIC 8
Project
ICE , Inha University

9. Applied Technology – FFT Algorithm
DFT Algorithm
FFT Algorithm (DECIMATION-IN-FREQUENCY)
- FFT is same as DFT using less computation times
- (Principle) DFT can be spilted as half
- applying the principle recursively, results in a computation that consists of butterflies only. ,
This is De
Bottom
Take
<Butterfly Unit>
Take notice of this multiplier
Project
ICE , Inha University

10. Applied Technology – FFT Algorithm
<Butterfly Unit>
Applied Technology – FFT Algorithm
Radix-2 16-Point FFT Algorithm (DECIMATION-IN-FREQUENCY)
This is De
Bottom
Take
We make Radix-2 64-Point FFT.
64-Point FFT is same this priciple.
Project
ICE , Inha University

11. Applied Technology – CORDIC Based FFT
CORDIC & FFT Similarity
Multiplier in FFT operation is same as CORDIC operation
<Butterfly Unit>
- Same operation.
- As a result FFT can be modified to
be more simple.
This So
This is
Project
ICE , Inha University

12. Applied Technology – CORDIC Based FFT
<Butterfly Unit>
Applied Technology – CORDIC Based FFT
CORDIC Based FFT Algorithm (CORDIC + FFT) v v c c
This So
This is
Multiplier
CORDIC
We make 64-Point FFT. 64-Point FFT is same this priciple.
Project
ICE , Inha University

13. Design flow 16/64 Point FFT C-Coding CORDIC Verilog Coding
Using Visual studio 2008 professional 2
CORDIC Verilog Coding
Using Xilinx ISE Design Suite 12.3 3
Radix-2 16-point CORDIC Based FFT Verilog Coding 4
Radix-2 64-point CORDIC Based FFT Verilog Coding 5
Radix-2 64-point Multiplier Based FFT Verilog Coding
Radix-2 64-point CORDIC Based FFT FPGA Implementation
Using Xilinx ISE Design Suite 12.3, Vertex 4
This So
This is
Project
ICE , Inha University

14. Progress Method- 16/64-Points FFT C-Coding
C-Language (SW) – 16/64-Points FFT C-Coding
For verification of Verilog result
This So
This is
Project
ICE , Inha University

15. Progress Method - CORDIC Verilog Coding
Diagram
CORDIC BLOCK Diagram
This So
This is
Project
ICE , Inha University

16. Progress Method - CORDIC Verilog Coding
CORDIC – Coding & Synthesis
This is de
Sixteen
Project
ICE , Inha University

17. Progress Method - CORDIC Verilog Coding
CORDIC Verification
16 clk
This So
This is
- Sin(30) = ≈ 1/2
- Cos (30) = ≈ √3/2
Project
ICE , Inha University

18. Progress Method – 16-Points CORDIC Based FFT Verilog Coding
Diagram
This So
This is
Project
ICE , Inha University

19. Progress Method – 16-Points CORDIC Based FFT Verilog Coding
Timing analysis
16 Delay
CORDIC
16 Delay
CORDIC
16 Delay
We analy
CORIC So
And
Total
Conse
Following
CORDIC
CORDIC
Project
ICE , Inha University

20. Progress Method – 16-Points CORDIC Based FFT Verilog Coding
Block Sketch & Condition Analysis
Top Block
우선 전체적인 모듈을 손으로 그려보았습니다. 각 와이어의 이름을 정해주고 인풋과 아웃풋의 연결을 정하였습니다.
Project
ICE , Inha University

21. Project Process – 16-Points CORDIC Based FFT Verilog Coding
Block Sketch & Condition Analysis
Sub Block &
Condition
세부 모듈을 손으로 그려 본 결과입니다. 여기서는 모듈 내에서의 인풋,아웃풋 값을 컨트롤 시그널인 카운트 값으로 부터 선택되어지게 만들었습니다.
Project
ICE , Inha University

22. Progress Method – 16Points CORDIC Based FFT Verilog Coding
Project
ICE , Inha University

23. Progress Method – 16-Points CORDIC Based FFT Verilog Coding
Synthesis
합성한 결과인 세부 블록도 이고 각 기능은 다음과 같습니다.
FFT_STAGE 1
FFT_STAGE 2
FFT_STAGE 3
FFT_STAGE 4
COUNT
DELAY
TEMPORARY
R O M
Project
ICE , Inha University

24. Progress Method – 16-Points CORDIC Based FFT Verilog Coding
Verification
<Verliog simulation>
기존 FFT의 기본 연산단위인 Butterfly Unit에서 Multiplier가 있습니다.
(클릭) 코딕 Module은 이 Multiplier를 대체 하게 됩니다.
CORDIC 알고리즘은 H/W구조가 매우 간단합니다. 그리고 곱셈기 연산에 비해 연산속도가 빠릅니다.
따라서 Size Speed Power의 개선이 이뤄집니다.
<C-coding verification>
Project
ICE , Inha University

25. Progress Method - 64-Points CORDIC Based FFT Verilog Coding
Diagram
This So
This is
Project
ICE , Inha University

26. Progress Method - 64-Points CORDIC Based FFT Verilog Coding
Timing analysis We
Eight
Based this result
Project
ICE , Inha University

27. Progress Method - 64-Points CORDIC Based FFT Verilog Coding
Block Sketch & Condition Analysis
CORDIC based FFT BLOCK Diagram
This So
This is
Project
ICE , Inha University

28. Progress Method - 64-Points CORDIC Based FFT Verilog Coding
Verification
This So
This is
Project
ICE , Inha University

29. Progress Method - 64-Points Multiplier Based FFT Verilog Coding
Timing analysis
For Comparison to our design of CORDIC Based FFT We
Eight
Based this result
Project
ICE , Inha University

30. Progress Method- 64-Points CORDIC Based FFT FPGA Implementation
Hardware Implementation (FPGA)
FPGA Board : Virtex4 – XCVLX60 – FFG668
기존 FFT의 기본 연산단위인 Butterfly Unit에서 Multiplier가 있습니다.
(클릭) 코딕 Module은 이 Multiplier를 대체 하게 됩니다.
CORDIC 알고리즘은 H/W구조가 매우 간단합니다. 그리고 곱셈기 연산에 비해 연산속도가 빠릅니다.
따라서 Size Speed Power의 개선이 이뤄집니다.
Project
ICE , Inha University

31. Progress Method- 64-Points CORDIC Based FFT FPGA Implementation
Hardware Implementation (FPGA)
FPGA Board : Virtex4 – XCVLX60 – FFG668
기존 FFT의 기본 연산단위인 Butterfly Unit에서 Multiplier가 있습니다.
(클릭) 코딕 Module은 이 Multiplier를 대체 하게 됩니다.
CORDIC 알고리즘은 H/W구조가 매우 간단합니다. 그리고 곱셈기 연산에 비해 연산속도가 빠릅니다.
따라서 Size Speed Power의 개선이 이뤄집니다.
Project
ICE , Inha University

32. Core Contents That Contributed
1. Replace complex Multiplier to CORDIC
- > Reduce Operation Time
멀티플라이어를 코딕으로 대체함으로써 FFT의 크리티컬 패쓰를 줄일 수 있었습니다. 그 결과로 전체 연산 시간이 줄어 들 것입니다.
CORDIC
Multiplexer
Project
ICE , Inha University

33. Core Contents That Contributed
2. Pipelined Architecture - > Reduce Clock Period
3. Single Path Delay Feedback - > Reduce Rom Size
파이프 라인 설계를 통해 클럭 주기를 줄일 수 있습니다. 이로 인해 전체 시간당 연산 량이 증가 될 것입니다.
또한 싱글패스딜레이피드백 방식을 통해 사용되는 롬의 크기를 줄일 수 있었습니다.
Project
ICE , Inha University

34. Hardware Implementation (FPGA)
Final Results
Hardware Implementation (FPGA)
(Radix-2 64-Points CORDIC based FFT vs Radix-2 64-Points FFT)
FPGA Board : Virtex4 – XCVLX60 – FFG668
Radix-2 64-Points
CORDIC based FFT (32bits)
Item
Specification
Slices
Number of Slices
18,353
Number of 4 Input LUTs
35,944
Timing Summary
Clock Period
7.995 ns
Clock Speed
MHz
Total # of paths
6,956,709
Destination Ports
33,824
Radix-2 64-Points FFT (32bits)
Item
Specification
Slices
Number of Slices
8,312
Number of 4 Input LUTs
14,839
Timing Summary
Clock Period ns
Clock Speed
30.302MHz
Total # of paths
564,46,741,023,767,814,000
Destination Ports
2,807
사이즈 약 2.2배
스피드 약 4.17배.
Project
ICE , Inha University

35. Conclusion & Next Research Subject
Operation Speed is faster than original FFT processor. Because CORDIC operation quantity is lower than multiplier. But our design isn’t perfectly efficient because our unripe design technic. So size is larger than original one. It is improved by some efficient design technic. So CORDIC based FFT that we make is useful at chip that high speed is required.
Research about how can we optimization of CORDIC based FFT.
< Next Research Subject >
멀티플라이어를 코딕으로 대체함으로써 FFT의 크리티컬 패쓰를 줄일 수 있었습니다. 그 결과로 전체 연산 시간이 줄어 들 것입니다.
Project
ICE , Inha University

36. Reference
[1] Dale Drinkard, “A highly configurable 1st quadrant CORDIC core in verilog” September 13, 2008 pp 1-6.
[2] Choudhary, Pooja, Karmakar, Abhijit "CORDIC based implementation of Fast Fourier Transform" 2011 pp
[3] Volder Jack E "The CORDIC Trigonometric Computing Technique" 1959 pp
[4] Ray Andraka "A survey of CORDIC algorithms for FPGA based computer", Proceeding of the1998 ACM/SIGDA sixth international symposium on Field programmalbe gate arrays, 1998, pp
[5] Alvin M. Despin "Fourier Transform Computer Using CORDIC Iterations.", IEEE Transcactions on Computers, 1974, pp
참고문헌은 위와 같습니다.
감사합니다.
Project
ICE , Inha University