Presentation is loading. Please wait.

Presentation is loading. Please wait.

Modulo-N Counters Module M10.4 Section 7.2.

Published byMateo Fett Modified over 9 years ago

Similar presentations

Presentation on theme: "Modulo-N Counters Module M10.4 Section 7.2."— Presentation transcript:

1 Modulo-N Counters Module M10.4 Section 7.2

2 Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout
Modulo-N Down Counter

3 Modulo-5 Counter s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D CLK D Q !Q Q0 Q0.D Q1 Q2 Q1.D Q2.D

4 Modulo-5 Counter Q1 Q0 s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 X X X 1 Q2.D Q2.D = Q1 & Q0

5 Modulo-5 Counter Q1 Q0 s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 X X X 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

6 Modulo-5 Counter Q1 Q0 s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 X X X 1 Q0.D Q0.D = !Q2 & ! Q0 Note: On reset output pins are all high. Therefore, we need to include a clear input.

7 mod5cnt.pld

8 mod5cnt.abl MODULE Mod5Cnt
TITLE ‘Modulo-5 Counter, A. Student, 7/20/02' DECLARATIONS “ INPUT PINS “ PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 " OUTPUT PINS " Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer'; " LED 6..8 Q = [Q2..Q0]; " 3-bit output vector [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display

9 mod5cnt.abl (cont’d) Note !Clear EQUATIONS Q.c = PB;
Q0.d = !Clear & !Q2 & !Q0; Q1.d = !Clear & !Q1 & Q0 # !Clear & Q1 & !Q0; Q2.d = !Clear & Q1 & Q0; DP = PB; " decimal point @radix 16; truth_table ( Q -> Segments ) " 7-segment display … Note !Clear

10 mod5cnt.abl (cont’d) @radix 16;
truth_table ( Q -> Segments ) " 7-segment display 0 -> 7E; 1 -> 30; 2 -> 6D; 3 -> 79; 4 -> 33; 5 -> 5B; 6 -> 5F; 7 -> 70;

11 mod5cnt.abl (cont’d) test_vectors([PB,Clear] -> Q) [.c.,1] -> 0;
END

12 Simulation File, mod5cnt.si
CUPL Simulation File

13 mod5cnt.si CUPL Simulation File Note: first test vector clears output
Back to LLL after 5 states

14 CUPL Simulation Output File

15 Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout
Modulo-N Down Counter

16 3-Bit Down Counter s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D CLK D Q !Q Q0 Q0.D Q1 Q2 Q1.D Q2.D

17 3-Bit Down Counter Q1 Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1 Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0

18 3-Bit Down Counter Q1 Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1 Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0

19 3-Bit Down Counter Q1 Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1 Q0.D Q0.D = ! Q0

20 dncnt3ld.abl If load = 1, Load Data to [q0..2]
MODULE DnCnt3LD TITLE '3-bit Down Counter with Clear and Load' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 Load PIN 11; " Switch 3 X2..X0 PIN 71,66,70; " Switch 6..8 Data = [X2..X0]; " 3-bit input vector " OUTPUT PINS " LED1..LED2 PIN 44,43 ISTYPE 'com'; " LED 1..2 timeout PIN 41 ISTYPE 'com'; " LED 3 Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer'; " LED 6..8 Q = [Q2..Q0]; " 3-bit output vector [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display If load = 1, Load Data to [q0..2] timeout = 1 when [q0..2] = [0,0,0]

21 dncnt3ld.abl (cont’d) EQUATIONS LED1 = Clear; LED2 = Load; Q.c = PB;
WHEN Clear THEN Q.d = 0; ELSE { WHEN Load THEN Q.d = Data; Q2.d = !Clear & !Q2 & !Q1 & !Q0 # !Clear & Q2 & Q1 # !Clear & Q2 & Q0; Q1.d = !Clear & !Q1 & !Q0 # !Clear & Q1 & Q0; Q0.d = !Clear & !Q0; } timeout = !Q0 & !Q1 & !Q2; …

22 Simulation File, dncnt3ld.si
CUPL Simulation File

23 dncnt3ld.si CUPL Simulation File ORDER:
clock,%2,clear,load,%3,I2..0,%3,q0,%2,q1,%2,q2,%2,timeout; VECTORS: C10 XXX LLL H /* clear counter */ C00 XXX HHH L C00 XXX LHH L C00 XXX HLH L C00 XXX LLH L C00 XXX HHL L C HLH L /* load 101 into counter */ C00 XXX HHL L C00 XXX LHL L C00 XXX HLL L C00 XXX LLL H /* timeout */

24 CUPL Simulation Output File

25 Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout
Modulo-N Down Counter

26 3-Bit Down Counter with Load and Timeout
______________ | dncnt3ld | clock x---| |---x Vcc clear x---| |---x q0 load x---| |---x q1 I0 x---| |---x q2 I1 x---| |---x timeout I2 x---| |---x x---| |---x x---| |---x x---| |---x GND x---| |---x |______________| To make a Modulo-5 counter, connect [I2..0] to 100 and connect timeout to load.

27 CUPL Simulation Output File

Download ppt "Modulo-N Counters Module M10.4 Section 7.2."

Similar presentations

Shift-Registers and Push Button Debounce

Shift-Registers and Push Button Debounce
Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders.

Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders.
Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN 0 0 0 0 1 0 YIN 0 0 1 0 0 0 YIN 0 1 1.

Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN
Shift Registers Module M11.1 Section 7.3.

Shift Registers Module M11.1 Section 7.3.
7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.

7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.
//HDL Example 6-1 //--------------------- //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.

//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.
How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.

How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.
Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.
7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.

7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.
Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp. 101-106.

Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp
Counter Circuits and VHDL State Machines

Counter Circuits and VHDL State Machines
Using State Machines as Control Circuits Lecture L9.4.

Using State Machines as Control Circuits Lecture L9.4.
Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)

Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)
Pulse-Width Modulated DAC

Pulse-Width Modulated DAC
Multiplexers Lecture L6.4 Section 6.4.

Multiplexers Lecture L6.4 Section 6.4.
Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.

Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.
Designing State Machines Lecture L9.2 Handout Section 9.2.

Designing State Machines Lecture L9.2 Handout Section 9.2.
Datapaths Lecture L10.2 Sections 10.2, 10.3. ALU (Sect. 7.5 and Lab 6)

Datapaths Lecture L10.2 Sections 10.2, ALU (Sect. 7.5 and Lab 6)
Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1.

Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.
Counters as State Machines Lecture L9.1 Handout Section 9.1.

Counters as State Machines Lecture L9.1 Handout Section 9.1.

Similar presentations

Ads by Google