1. Low Power Design for a 64 point FFT Processor
Arish Alreja

2. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
Overview
We will discuss
Motivation
Fourier Transforms and FFTs (briefly)
A low power 64 point FFT Processor.
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

3. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
Motivation
Orthogonal Frequency Division Multiplexing (OFDM) is used in a WiFi chipsets to achieve higher resiliency against errors due to multipath fading by encoding data over multiple carrier frequencies
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

4. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
Motivation
FFT is the most computationally intensive part of OFDM
802.11a WiFi standard requires 64 point FFT for OFDM
Low Power FFT improves battery life on mobile devices
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

5. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
Fourier Transforms
Fourier Transforms allow Frequency Domain
representation of a signal in the Time Domain.
Time Domain
Frequency Domain
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

6. Computation Discrete/Digital FT X(ej) =  x[n]* e-jn DFT Algorithm
O(n2) [Blue]
X(ej) =  x[n]* e-jn
With some Mathematical rearrangements we get the Fast Fourier Transform
Algorithm
FFT Algorithm O(nlog2n) [Red]
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

7. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
FFT Complex Butterfly
The basic operation in the FFT algorithm is the Complex Butterfly calculation.
Am-1
Bm-1 Am Bm -1 W
Am= (Am-1 + Bm-1)/2
Bm= (Am-1 - Bm-1)*W/2
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

8. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
FFT Complex Butterfly
Am-1
Bm-1 Am Bm -1 W
1. Why do we divide by 2?
To avoid arithmetic overflow
2. What is W ?
W is the constant “twiddle factor”
3. What are A & B?
A and B are the terms that are undergoing the computation (In Place computation)
4. What is m?
“m” represents the resulting stage of the FFT
K = 0:N/2-1
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

9. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
Radix 8 FFT Flow Graph
X[0]
X[1]
X[2]
X[3]
X[4]
X[5]
X[6]
X[7]
Y[0]
Y[4]
Y[2]
Y[6]
Y[1]
Y[5]
Y[3]
Y[7]
M = 1
M = 2
M = 3
Bit reversal of indexes after in place computation
Time Domain
Frequency Domain
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

10. Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)
Radix 64 FFT Flow Graph
Arish Alreja: Low Power Design for a 64 Point FFT Processor (2006)

11. Arish Alreja: Low Power Design for a 64 Point FFT Processor
FFT Computation
64 point FFT => 6 stages [log2(n)]
Each stage => 32 Butterfly computations
1 Butterfly computation
1 complex multiplication
2 complex additions
We have 32 constants
k= 0-31;(0-N/2-1)
Arish Alreja: Low Power Design for a 64 Point FFT Processor

12. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Design Constraints
Focus on low power consumption
1. Reduce memory Reads/Writes
Keep Data in Pipeline longer
2. Eliminate Digital Multiplier
64 point FFT => 32 constants (W’s).
Achieve multiplication with known constants by using combination of shifters and adders
Arish Alreja: Low Power Design for a 64 Point FFT Processor

13. Processor Datapath Mem Out Mem In Register File 2 Register File 1
D_Input Register Select
Butterfly Processor
Mem In
Input Register Select
Register File 1
Register File 2
RS1
RS2
D_RS1
D_RS2
ChooseMemReg
Mem Out
Arish Alreja: Low Power Design for a 64 Point FFT Processor

14. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Radix 64 FFT Flow Graph
Memory Read
Memory Write
Memory Read
Memory Write
Stages
Register Write
Register
Read
Register
Read
Register
Read
Register Write
Register Write
Register
Read
Register
Read
Register Write
Register Write
Register
Read
Register Write
Arish Alreja: Low Power Design for a 64 Point FFT Processor

15. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Butterfly Processor B A
Adder
Wire
(A+B)/2
(A-B)W/2
CSD3
CSD 5
CSD 7
CSD2
CSD 4
CSD6
CSD8 32
CSD11
CSD10
CSD 12
Multiplier Block 1
CSDB1
3 bit
Multiplier Block 2
CSDB2
2 bit
Arish Alreja: Low Power Design for a 64 Point FFT Processor

16. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Constants
k= 0-31; (0-N/2-1) [ 32 constants]
1. In the design we have to hardcode only 10 constants, because
2. Also, we exploit the property to achieve any twiddle factor from using only the following 10 hard coded constants
Multiplier Block 2
Multiplier Block 1
Arish Alreja: Low Power Design for a 64 Point FFT Processor

17. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Concluding Remarks
Design lowers power consumption by
Eliminating full Digital Multiplier by using combination of shifters/adders to implement multiplication with 32 constants
32 constants can be realized by combining 10 actual constants
1/3rd reduction in memory access
Implementation and testing done in Verilog HDL. Results cross-checked against MATLAB reference implementation.
Arish Alreja: Low Power Design for a 64 Point FFT Processor

18. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Acknowledgements
Dr. Vijay Madisetti: Faculty Mentor
Mohanned Sinnokrot: Graduate Mentor
Code generation
tool for optimal number of shifters and
adders for multiplier constant multiplication
blocks.
Arish Alreja: Low Power Design for a 64 Point FFT Processor

19. Arish Alreja: Low Power Design for a 64 Point FFT Processor
Questions ?
Arish Alreja: Low Power Design for a 64 Point FFT Processor