Determining the Optimal Process Technology for Performance- Constrained Circuits Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5.

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Presentation transcript:

Determining the Optimal Process Technology for Performance- Constrained Circuits Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5 th, 2006

Outline Motivation Methodology Related work Results Conclusion

Performance Classes 1.Unconstrained –General-purpose microprocessors 2.Constrained –Digital signal processors –Many embedded devices Relation to technology scaling

Methodology Build circuit in multiple technologies Vary supply voltage and measure: –Delay –Active power –Leakage power Vary duty cycle and frequency and compute minimum power

Circuit

PTM Threshold Voltages TechnologyVth0nVth0p 130nm nm nm nm nm

Total Power Calculation = activity factor T = circuit delay T target = maximum delay = 1 / frequency

Related Work 1995: Minimizing Power Consumption in Digital CMOS Circuits –Chandrakasan & Brodersen 2005: An Ultra Low Power System Architecture for Sensor Network Applications –Hempstead, et al

Conclusion 0.6um best choice for low duty cycle, low frequency operation Problems: –PTMs –1.6um

References S. Borkar, “Design Challenges of Technology Scaling”, IEEE Micro, vol. 19, no. 4, pp , A. Chandrakasan and R. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp , M. Hempstead, et al, “An Ultra Low Power System Architecture for Sensor Network Applications”, Proceedings of the 32nd International Symposium on Computer Architecture, Y. Cao, et al, “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation”, CICC, pp , C. Hu, “BSIM Model for Circuit Design Using Advanced Technologies”, Symp. VLSI Circuits, pp. 5-6, 2001.