CORTEX-M0 Structure Discussion 2 – Core Peripherals ARM Cortex-M0 CORTEX-M0 Structure Discussion 2 – Core Peripherals August 22, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com

Cortex-M0 Structure Discussion 2 – Core Peripherals Topics Today CORTEX-M0 SYSTICK Core Peripheral CORTEX-M0 NVIC Core Peripheral CORTEX-M0 SCB Core Peripheral

Cortex-M0 Core Peripherals Cortex-M0 32 Bit CPU SYSTICK NVIC SCB Core Peripherals are Common to All Cortex Devices

Core Peripheral Memory Map Memory Region Usage Memory Attribute XN Memory Region Start Memory Region Stop Device Access Device 0xE0100000 0xFFFFFFFF Private Peripheral Strongly Ordered 0xE0000000 0xE00FFFFF External Device 0xA0000000 0xDFFFFFFF External Memory Normal -- 0x60000000 0x9FFFFFFF Internal Peripheral 0x40000000 0x5FFFFFFF Internal SRAM 0x20000000 0x3FFFFFFF Internal Code Execute 0x00000000 0x1FFFFFFF

Core Peripheral Memory Map Memory Region Start Memory Region Stop Nested Vector Controller (NVIC) 0xE000EF00 0xE000EF03 System Control Block (SCB) 0xE000ED00 0xE000ED3F 0xE000E100 0xE000E4EF SysTick Timer (STK) 0xE000E010 0xE000E01F 0xE000E008 0xE000E00F

SYSTICK Core Peripheral Cortex-M0 CPU System Clock SysTick Interrupt 24-Bit Reload Register IRQ Control Register 24-Bit Down Counter

SYSTICK Core Peripheral P e r i o d i c I n t e r r u p t s time Time interval = Reload Count / Clock Frequency

SYSTICK Core Peripheral Simple Periodic Interval Timer Identical Structure in Cortex-M0, M3, M4 Settable Interrupt Priority 24-Bit Counter Width Count Enable Control Interrupt Enable Control

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is an Interrupt Controller? INSTRUCTION Normal Program Flow Instruction Proceed in Sequence

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is an Interrupt Controller? INSTRUCTION INSTRUCTION Interrupt Event Normal Program Flow Interrupt Service Program Flow Interrupt Return

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is an Interrupt Controller? An Interrupt Controller manages the process of interrupting normal program flow upon receipt of an interrupt event Interrupt Entry: Push Stack Frame Fetch Interrupt Vector Interrupt Exit: Pop Stack Frame Resume normal program execution

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Vectored’ Interrupt Controller? Vector Table contains Start Address of Interrupt Service Routine Vector Table Interrupt Controller Interrupt Service Routine 2 VECTOR 0 VECTOR 1 VECTOR 2 VECTOR 3 VECTOR 4 VECTOR 5 VECTOR 6 VECTOR 7 VECTOR 8 VECTOR N Interrupt Service Routine 8 Individual Interrupts Interrupt Service Routine 4 Interrupt Service Routine 6

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Vectored’ Interrupt Controller? An Interrupt Vector is a unique 32-Bit value which is set to the Start Address of an Interrupt Service Routine Interrupt Vectors are Stored in a Sequential Table of Vectors Vectored Interrupts have low latency

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Vectored’ Interrupt Controller? Exception Number IRQ Number Vector Offset Initial Stack Value 0x00 1 Reset Vector 0x04 2 -14 NMI Vector 0x08 3 -13 Hard Fault Vector 0x0C 4 RESERVED 5 6 7 8 9 10 11 -5 SVCall Vector 0x2C 12 13 14 -2 PendSV Vector 0x38 15 -1 SYSTICK Vector 0x3C 16 IRQ0 Vector 0x40 17 IRQ1 Vector 0x44 18 IRQ2 Vector 0x48 47 31 IRQ31 Vector 0xBC

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Vectored’ Interrupt Controller? NOT VECTORED VECTORED Normal Program Flow Normal Program Flow Has extra steps longer latency Receive Interrupt Receive Interrupt Branch to Global Service Routine Service Unique Interrupt Service Unique Interrupt Determine Unique Interrupt Return to Normal Program Flow Return to Normal Program Flow Older ARM7 Style New CORTEX Style

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Low Priority High Priority INSTRUCTION INSTRUCTION INSTRUCTION Interrupt Event Interrupt Event Normal Program Flow Interrupt Service Program Flow Interrupt Service Program Flow Interrupt Return Interrupt Return

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Nested Interrupt Support Individual Interrupts have Priority Higher Priority Interrupt will Preempt Lower Lower or Equal Priority Interrupt will Wait Interrupt Tail Chaining to Reduce Latency Interrupt Late Arriving to Reduce Latency

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Interrupt Types Interrupt Priority Reset Highest Priority -3 Non Maskable Interrupt (NMI) Priority -2 Hard Fault Priority -1 SVCall Configurable Priority PendSV SysTick Interrupt (IRQ0 - 31)

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Interrupt Preemption Higher Priority Interrupt preempts lower priority interrupt Interrupt Tail Chaining At completion of interrupt, it another interrupt event has occurred, then stack pop is skipped and new interrupt service starts Interrupt Late Arriving If low priority interrupt begins and while saving the stack frame a higher priority interrupt occurs, then higher priority interrupt will execute first.

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Int Push Stack Frame Service Interrupt Pop Stack Frame Normal program flow Normal program flow Int 1 Int 2 Service Interrupt 1 Service Interrupt 2 Service Interrupt 1 Push Stack Frame 1 Push Stack Frame 2 Pop Stack Frame 2 Pop Stack Frame 1 Normal program flow Normal program flow Interrupt Preemption – Int 2 Higher Priority Than Int 1

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Int Push Stack Frame Service Interrupt Pop Stack Frame Normal program flow Normal program flow Int 1 Int 2 Service Interrupt 2 Push Stack Frame Service Interrupt 1 Pop Stack Frame Normal program flow Normal program flow Interrupt Tail Chaining – Int 1 Higher or Equal Priority Than Int 2

Nested-Vectored Interrupt Controller NVIC Core Peripheral What is a ‘Nested’ Vectored Interrupt Controller? Int Push Stack Frame Service Interrupt Pop Stack Frame Normal program flow Normal program flow Int 1 Int 2 Service Interrupt 1 Push Stack Frame Service Interrupt 2 Pop Stack Frame Normal program flow Normal program flow Interrupt Late Arriving – Int 2 Higher Priority Than Int 1

SCB Core Peripheral Register Set which provides system implementation and system control functions CPU ID Register Interrupt Control and State Register Application Interrupt and Reset Control Register System Control Register Configuration Control Register System Handler Priority Registers

Cortex-M0+ Peripheral MPC Core Peripheral Memory Protection Unit CORTEX-M0+ Eight Separate Regions CORTEX-M0+ Overlapping Regions CORTEX-M0+ Background Regions

Meaning and Implications 32 Bit CORTEX-M0 Processing Capability Sophisticated NVIC Interrupt Control Low Latency Interrupt Features Vectoring, Preemption, Chaining, Late Arrival Core Control Features Memory Protection Unit 8 Bit Architecture Processor Architecture – 8 Bit World to 32 Bit World