1 Interrupts INPUT/OUTPUT ORGANIZATION: Interrupts CS 147 JOKO SUTOMO
2 Why we need Interrupts? Input/output devices are slower than memory and CPU. Different device requires different amount of time from CPU. Uncertainty of when device will be ready.
3 Modes of Data Transfer Polling Wait States Interrupts
4 Continuously checking the status of a peripheral; e.g. read data from an input keyboard. Polling is relatively straightforward in design and programming with the sacrifice of system performance. Polling
5 Wait States If a device assert wait signal, the CPU: stays in wait states outputting the address of I/O device outputting value of control signal.
6 Data Transfer With Interrupt 1) When a peripheral is ready it sends an interrupt signal the the CPU 2) The CPU stops execution of the program 3) Accepts data from peripheral 4) Returns to the interrupted program
7 Types of Interrupts There are three types of interrupts, each with several different uses: External Interrupts Internal Interrupts Software Interrupts Procedures for processing all types of interrupts are almost identical
8 External Interrupts Used by CPU to interact with input/output devices; e.g. the CPU requests a data transfer and in input device asserts an interrupt when it is ready. Improve system performance by allowing the CPU to execute instructions. Also used to initiate transfers.
9 Internal Interrupts Occurs entirely within the CPU Used to handle exception that occur during the execution of valid instructions; e.g: Divide by zero exception Arithmetic overflow Page faults Invalid instruction codes
10 Software Interrupts Generated by specific interrupt instructions in the CPU’s instruction set. These interrupt act like subrutine call statements except they always go to a specific address.
11 Processing Interrupts These events only occur if the interrupt is enabled. A handler (software to service the interrupt) is executed. CPU returns to where it left off in the main program.
12 Classification Maskable Interrupt Can be ignored by the CPU Non-maskable Interrupt Cannot be disabled, always handled. CPU responds immediately Highest priority among interrupts
13 Handler Handler is essentially a subroutine. There may be one handler routine for each interrupt or one unified handler routine for all interrupts.
14 Handler Handler (cont.) If handler routine is interrupted part way through: Save the contents of internal registers of the CPU Save the state information within Control Unit
15 Handler Handler (cont.) To illustrate, consider this execute routine for the LDAC instruction for the Relatively Simple CPU LDAC1: DR M, PC PC+1, AR AR+1 LDAC2: TR DR, DR M, PC PC+1 LDAC3: AR DR, TR LDAC4: DR M LDAC5: AC DR
Handler Handler (cont.) When the CPU accesses the handler routine, the following steps are performed: CPU pushes the current value of the program counter (PC) onto stack CPU loads the address of the handler routine into the PC. The handler routine then performs its tasks. When it finished, it returns to the correct location by popping the value of the PC off the stack
17 Getting the Address of the Handler Routine Vectored Interrupts Non-vectored Interrupts
18 Vectored Interrupts Vectored interrupts supply the CPU with information, the interrupt vector, which is used to generate the address of the handler routine for the interrupt. Useful for CPUs that receive interrupt request from several devices via the same control line.
19 Non-Vectored Interrupts A non-vectored interrupt uses a handler routine at a known address. CPU does not need any additional information to generate this address and access its handler routine.
20 For Non-vectored Interrupt Request: An external device sends an interrupt to the CPU by asserting its IRQ signal. When CPU is ready, it asserts its interrupt acknowledge signal (IACK), The device sets IRQ low, which cause CPU to set IACK low. Handler routine proceeds and starts transferring data.
21 (a) Hardware and (b) timing for a nonvectored interrupt for a single device
22 For Vectored Interrupt Request: External device sends interrupt to the CPU by asserting its IRQ signal. CPU inputs an interrupt vector from the device and call an interrupt service routine (handler) The device sets IRQ low Handler routine proceeds and starts transferring data.
23 (A) Hardware and (B) Timing for a Vectored Interrupt for a Single Device
24 Prioritizing Multiple Interrupts Extension of the nonvectored interrupt hardware Daisy chaining Parallel priority
25 Extension of the nonvectored Interrupt Hardware for multiple nonvectored interrupts
26 Priority of Multiple nonvectored Interrupts IRQn has the highest priority and IRQ0 has the lowest. E.g. IRQ 7 Has higher priority than IRQ 5.
27 Extension of the nonvectored Interrupt: Extension of the nonvectored Interrupt: Implementation Issues This method works well when there are only a few IRQ/IACK pairs. Number of pins needed by CPU to accommodate signals become prohibitive.
31 Parallel Priority Implementing priority Interrutps in parallel
32 Parallel Priority Advantage: All interrupt requests require the same amount of time. Priority of the device does not determine the time needed to acknowledge the interrupt. Disadvantage: The system is much more difficult to expand than the daisy chain configuration.
33 Thank You Joko Sutomo CS 147 Prof. Sin-Min Lee