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ARM Cortex-M3 RTLAB 박 유 진.

Published byDulcie Eugenia Powell Modified over 6 years ago

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Presentation on theme: "ARM Cortex-M3 RTLAB 박 유 진."— Presentation transcript:

1 ARM Cortex-M3 RTLAB 박 유 진

2 Main features High performance & Low energy consumption
Thumb-2 assembly language Advanced Interrupt Handling Nested Vectored Interrupt Controller(NVIC) Efficiency Memory Map & BUS Interface Big-endian, Little-endian mode Non-aligned memory access

3 Registers R0 R13(MSP) R13(PSP) Stack registers R1 R14(LR)
Link registers R2 R15(PC) Program Counter R3 Upper registers R4 R5 xPSR Program Status R6 General purpose registers PRIMASK R7 FAULTMASK Interrupt Mask register R8 BASEPRI R9 R10 Lower registers CONTROL Control register R11 R12

4 Operation Mode Privilege handler Exception Terminate Default Exception
thread Exception Exception Terminate User thread

5 Nested Vectored Interrupt Controller : NVIC
Nested Interrupt Handling Vectored Interrupt Handling Dynamic Priority Configuration Interrupt Masking

6 Nested Vectored Interrupt Controller : NVIC
Vector table No Offset Exception Vector 0x48 – 0x3FF IRQ #2-239 7-10 0x1C – 0x28 Reserved 17 0x44 IRQ #1 6 0x18 User fault 16 0x40 IRQ #0 5 0x14 Bus fault 15 0x3C System tick 4 0x10 MemManage fault 14 0x38 Pend SV 3 0x0C Hardware fault 13 0x34 2 0x08 NMI 12 0x30 Debug monitor 1 0x04 Reset 11 0x2C SVC 0x00 MSP Starting Point

7 Memory Interface Static BUS Interface Bit-band operation
Peripheral Unit(1MB) SRAM(1MB) Non-aligned Memory Access Big-endian & Little-endian mode System Level (0.5GB) External Peripheral Unit (1GB) External RAM Peripheral Unit(0.5GB) SRAM(0.5GB) Code(0.5GB) 0xFFFFFFFF 0xE 0xDFFFFFFF 0xA 0x9FFFFFFF 0x 0x5FFFFFFF 0x 0x3FFFFFFF 0x 0x1FFFFFFF 0x

8 Further Works Thumb-2 Assembly Language Interrupt Operation
Debugging Component Porting application from ARM to Cortex-M3

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