Status and planning of the CMX Philippe Laurens for the MSU group Level-1 Calorimeter Trigger General Meeting, CERN May 24, 2012

CMX: CMM upgrade CMX replaces CMM: 1) JEM/CPM to CMX (backpl) rate 40 →160Mbps 2) Crate CMX to System CMX (cables) rate 40 →160Mbps 3) Cluster information sent to Topological Processor (12- fiber 4) Optional partial TP capability included Standalone TP is now planned Some TP capability still desired for CMX platform (flexibility) 23/05/2012CMX status and plans 1

The CMX overview VME-- Interface TP-CMX FPGA Virtex-6 LX550T-FF1759 TP-CMX FPGA Virtex-6 LX550T-FF1759 Base-CMX FPGA Virtex-6 LX550T-FF1759 Base-CMX FPGA Virtex-6 LX550T-FF x Optic OUT 12x Optic IN DAQ ROI DAQ ROI TCM Interface VME-- TCM Inputs from all JEM or CPM processors from this crate LVDS cables From Crate To System CMX 400 single 160Mbps 3x27 LVDS up to 160 Mbps 2x 12-fiber ribbons OUT 3x 12-fiber ribbons IN 6.4 Gbps outputs to Standalone TP and/or TP-CMX 2x G-Link Out 6.4 Gbps inputs re-bundled from up to 12 Base-CMX CTP output 2x33 LVDS 40 Mbps (from TP-CMX via Base-CMX) 23/05/2012CMX status and plans 2

CMX: modular design, most cards assembled without TP functionality VME-- Interface Base-CMX FPGA Virtex-6 LX550T-FF1759 Base-CMX FPGA Virtex-6 LX550T-FF x Optic OUT DAQ ROI TCM Interface VME-- TCM Inputs from all JEM or CPM processors from this crate LVDS cables From Crate To System CMX 400 single 160Mbps 3x27 LVDS up to 160 Mbps 2x 12-fiber ribbons OUT 6.4 Gbps outputs to Standalone TP and/or TP-CMX 2x G-Link Out CTP output 2x33 LVDS 40 Mbps (System CMX only) 23/05/2012CMX status and plans 3

CMX: Use scenario with standalone TP ElectronEnergyJetTau Base- CMX FPGA Base- CMX FPGA to CTP LVDS Cables to CTP Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA LVDS Cables LVDS Cables LVDS Cables Optical Patch Panel Optical Patch Panel Crate CMXs System CMXs to CTP Standalone Topological Processor Standalone Topological Processor N x x 12-fiber ribbons 12 1 x 12-fiber ribbon 23/05/2012CMX status and plans 4

CMX development work on 3 fronts 3 parallel efforts CMX Philippe, Dan, and Chip CMX input module Wojtek and Yuri VME/ACE/TTC (VAT) Yuri CMX development schedule from Stockholm Preliminary Design Review is still valid Minor adjustments 23/05/2012CMX status and plans 5

CMX development schedule from PDR 2011: Project and engineering specifications CMX project Preliminary Design Review (done) Preliminary engineering design studies (done, RAL review) Test rig installed, checked out at MSU (postponed until 2012) 2012: Prototype design and fabrication CMX schematics and PCB layout (ongoing) CMM firmware ported to CMX Prototype fabrication (fall 2012) Basic tests for backward compatibility in test rig at MSU Production Readiness Review 2013: Prototype testing/installation/commissioning, final CMX fabrication Full prototype tests in test rig at CERN CMX firmware development and test Test in the L1Calo system during shutdown Fabricate and assemble full set of Final CMX (bulk with just Base, few with TP) 2014: Final commissioning in the L1Calo trigger system in USA15 23/05/2012CMX status and plans 6

23/05/2012CMX status and plans 7 CMX development timeline

: Prototype design and fabrication  CMX schematics and PCB layout CMX technology choice with Dual FPGA design: Base-CMX & TP-CMX (RAL Feb 2012) 6U VME test card for VAT interface (PCB ready for testing in June) Real-time data path layout (ongoing) CMX input module firmware currently under test on the XILINX development module Power budget estimate Prototype fabrication mechanical testing Blank card, backplane connectors, front panel tests. Will happen before real prototype board, but not urgent yet. CMM firmware ported on CMX Firmware for VAT interface (2 CPLD + TTC FPGA) to Spartan-3AN FPGA (Adapt VHDL code, create test bench, specify VME register model) (Yuri) Most of CMM data path work completed at Stockholm (Pawel Plucinski, Sam Silverstein) Needs to be adapted to final package choice Basic tests for backward compatibility in test rig at MSU Production Readiness Review (L1Calo/TDAQ) Fall/Winter PRR after the prototype(s) is tested and final check before going into full production of final modules 23/05/2012CMX status and plans 8

2012: PCB layout: VME/ACE/TTC (VAT) interface test card VME/ACE/TTC (VAT) part of CMM Redesign HW with new components Fit design into single device 6U VME test card for Hardware implementation Main FPGA re-configuration Software To be merged into CMX design PCB arrives in June Next: Firmware for VAT card Firmware for Virtex 6 FPGA Test Stand and software VME CPLD TTC FPGA ACE CPLD SystemACE TTCrx FC TTCDec Spartan-3AN VME-- logic CF SystemACE JTAG TTC Connector for CANbus i/f Virtex6 Power 5V0 3V3 2V5 1V0 3V32V51V0 1V2 23/05/2012CMX status and plans 9

2011/2012: design studies: Clock/parity recovery Clock+Parity encoded on single line Variable duty cycle Setup: Scheme tested using Virtex 6 eval board Data capture developed, simulated and ‘Placed and Routed’ on target FPGA Needs repeating – different package chosen Clock/parity Regional clock buffer (BUFR) MMCM Data 40 MHz BUFR 80 MHz BUFIO IDDR 40MHz register 96 40MHz x 16 23/05/2012CMX status and plans 10

2012 PCB Layout: Backplane – FPGA connection Optimize Real-Time Path Layout High local density near FPGA Especially 400x JEM/CPM inputs Spread out & mixed up on backpln  grouped & sorted at FPGA Span neighbor IO blocks Regional Clock input for clock/parity Tune IO Assignments Cleanest connections: no extra via Minimize number of trace layers 23/05/2012CMX status and plans 11 NOT FINAL In Parallel with Firmware design Validate assignment Timing constraints

Conclusions Original schedule is maintained With minor adjustments Prototype effort proceeding in parallel on 3 fronts according to plan Will need to increase level of detail for set of steps during in-situ tests before and after first beam Optimistic outlook 23/05/2012CMX status and plans 12