Design of LNA at 2.4 GHz Using 0.25 µm Technology Marco Donadio MSICT – RF Communication SoC

Paper Design of LNA at 2.4 GHz Using 0.25 µm Technology: by Xiaomin Yang, Thomas Wu and John McMacken University of Central Florida, School of E.E. implementation of 2.4 GHz CMOS low noise amplifier in a 0.25 µm technology single ended configuration fully integrated circuit, without off-chip components trade-off Power-supply vs figure of merit

Introduction What is an LNA? A circuit used to provide gain where preserving the signal-to-noise ratio is important Where can I find one? In wireless/wireline receivers and sensor interfaces Why ultra-low-power? Want a long battery life for portable/remote applications and implants

PAPER’S IMPLEMENTATION Inductive degeneration topology is used to get better noise performance for the narrow band applications. The amplifier has the commonly used cascode architecture wich provide a good isolation between the input and output stages. Ls and Lg are used to make impedence matching at the input, while the output impedence matching can be obtained by tuning the third inductor LD and the capacitor Cout.

Design Methodology Cascode Common-Source Cascode Design: Lg, Ls, Ld, Cm, Ctune, VB, VGS1, W1/L1, W2/L2 Problems with common-source - Low device output resistance  low gain - Poor input/output isolation  Instability

Paper’s Implementation LNA specification 0.25 µm technology 3.3 V supply gain about 15 dB noise figure of 2.2 dB power dissipation of 7.2 mW S11 = -17 dB S12 = -24 dB S21 = 15 dB S22 = -23 dB IIP3 = 1.3 dBm

PAPER’S IMPLEMENTATION DESIGN OF THE LNA Both the input and the output impedence are required to be 50 Ω. The first step is to determine the MOS transistor size in the input stage; the optimum device width for the authors is 200 µm to minimize noise figure. INPUT MATCH Input impedence is calculated as: where R1 is the series resistance of the gate of inductor and Rg is the gate resistance of the NMOS transistor M1. where R is the sheet resistance of the poly silicon, W is the total width of the device, L is the gate length and n is the number of gate fingers used to lay out the device Ls is determined

PAPER’S IMPLEMENTATION DESIGN OF THE LNA At the central frequency 2.4 GHz, the imaginary term of Zin will be zero, wich gives: From this equation, Lg is solved

MY IMPLEMENTATION Step1: MOS transistor technology features CTH technology (0.25 µm) Cox 8.4 fF/um^2 L 0.25 Kn’ 3.75e-04 A/V^2 Vth 0.45 LD 1e-02 um Cgdo 2.4e-16F/um Gamma 0.9 Delta 6 C 0.395 Alpha 1.3

MY IMPLEMENTATION Step2: Impedence matching Small-signal model (design Lg, Ls value to create a 50 Ω input impedence) Small-signal model Choose a small value of Ls (1.4nH) because it can be realized as a integrated inductor. Find the unity gain frequency gm/Cgs = ωT = 3.57e10 sec^-1 from the condition :

MY IMPLEMENTATION Step3: Optimal transistor size 3. Knowing transistor paramiters alpha, delta and gamma I found the parameter p = 2.253 and the optimal value of QL = 1.2 from: 4. Using the value of operating frequency ω0 I computed = 1.6nH 5. Finally I found the optimal value for the device width where = 1.467e-12 F

In the paper’s implementation W = 200 µm MY IMPLEMENTATION Considerations about optimal W In the paper’s implementation W = 200 µm W = 840 µm big transistor size, that means high power consumption

Transistor Sizing for Noise Cascode Common-Source NFLNA [dB] W [μm] NF of LNA improves with larger W However, power proportional to W  Noise-power tradeoff

MY IMPLEMENTATION Final Design of LNA

Simulations and results S12 S21 Parameters Gain at 2.4 GHz is 21.5 dB Reverse isolation gain is - 42.5 dB

Simulations and results Input Matching S11 Parameter Input matching at 2.4 GHz is -12 dB The initial value for S11 was about 7 dB, playing with Lg value I provided 12 dB (optimizer tool).

Simulations and results Output Matching S22 Parameter Output matching at 2.4 GHz is <-14 dB This value of S22 is obtained adding buffer stage at to output; without this stage output matching value was too bad, about -3 dB.

Simulations and results Noise Figure Parameter Noise Figure is very good (1 dB) This is intuitive because high power consumption (big W value)!!!!!!!

Simulations and results Intermodulation Distortion IIP3 Distortion is measured by applying two pure sinusoids with frequencies well within the bandwidth of the circuit (f1 and f2). The harmonics of these two frequencies would be outside the bandwidth of the circuit, however there are distortion products that fall at the frequencies 2f1 – f2, 2f2 – f1, 3f1 – 2f2, 3f2 – 2f1, etc.

Simulations and results 1dB Compression Point 1 dB compression point is the point at which the actual gain is 1 dB below the ideal linear gain

Simulations and results Power Consumption 23 mW

Conclusions Comparison between paper and our implementation: Input matching my S11= -15 dB vs paper’s S11 = -17 dB acceptable  Output matching my S22= -14.7 dB vs paper’s S11 = -23 dB Bad  Gain and revers isolation my S21= -21.5 dB vs paper’s S21 = -15 dB GOOD  my S12 = -42.5 dB vs paper’s S12 = -24 dB acceptable  Noise figure my NF = 1 dB vs paper’s NF = 2.2 dB GOOD  Power Consumption my PC = 23 mW vs paper’s PC = 7.2 mW TOO BAD !!! 

Future Improvements Output Matching: - Implement a new output matching network in order to achieve the S22 required. Power Consumption: Implement a new LNA with a 1.8 power supply. Use of capacitors in parallel to cascode stage to minimize width of transistors.