1. Distributed Power Amplifiers-Output Power and Efficiency Considerations Prasad N. Shastry (S. N. Prasad) 1, Senior Member, IEEE, and Amir S. Ibrahim 2 1 Department of Electrical and Computer Engineering, Bradley University, Peoria, IL, 2 Mobile Devices, Motorola Inc., Libertyville, IL

2. Abstract In this paper the efficiency and output power limitations of distributed amplifiers (DAs) and techniques to overcome the limitations are addressed, and the analysis, design, and measured results of a tapered drain line distributed power amplifier are presented in detail for the first time. The DA has a gain of 10 dB, power-added-efficiency of 24%, and output power of about 20 dBm, over a 4.5 GHz bandwidth. Further, the efficiency of the tapered drain line DA is shown to be comparable to a reactively matched power amplifier using the same number and type of transistors. The topology of the tapered drain line DA is suitable for monolithic implementation. Tapered drain line, conventional gate line- distributed power amplifier. Logical construction of the drain line of the tapered drain line of a distributed amplifier. Gain Comparison Between DAs, Reactively Matched Amplifiers, and Tapered Drain Line DAs PAE (%) Comparison Between DAs, Reactively Matched Amplifiers, and Tapered Drain Line DAs P1dB Comparison Between DAs, Reactively Matched Amplifiers, and Tapered Drain Line DAs http://cegt201.bradley.edu/rfpage Power and efficiency limiting factors in a distributed amplifier Transistor pinch-off Unequal contribution by transistors to output power Transistor gate-drain breakdown Un-utilized power in the reverse wave Non-optimum load impedance presented to transistors Tapered drain line distributed amplifier Each transistor must see its optimal load impedance, R OPT. Drain line consists of line segments of varying characteristic impedance connected between the output terminals of the cells. The characteristic impedance of the line segment between cells “m” and “m+1” is given by, Z om = R OPT /m. Gate line is designed as in a conventional lowpass distributed amplifier. Simulation Results and Analysis Transistor : NE721; Number of transistors : 4; Frequency range: 0-4.5 GHz; DC-Bias for each transistor: V ds = 3V; V gs = -0.675V; I ds = 30 mA. Conventional lowpass distributed amplifier: Image impedance of gate and drain lines: 50 Ω. Reactively matched balanced amplifier: Optimum load and source impedances at 2 GHz: Z L = 56.32 + j14.43 Ω; Z S = 62.02 + j59.67 Ω Tapered drain line distributed amplifier: Optimum load impedance (R OPT ) presented to each transistor: 50 Ω Image impedance of gate line : 50 Ω Wideband output matching network-to convert 50 Ω to 12.5 Ω (R OPT /4) Delays on the drain line equal the delays on the gate line. No termination on the drain line.

3. Distribution of power on the drain line for a tapered drain line DA Layout of the amplifier with output matching network Picture of the amplifier (including the heat sink) Plot showing simulated and measured magnitudes of S21. Measured gain compression at three different frequencies. Conclusions A tapered drain line DA having a gain of 10dB and power-added efficiency of 24% over a 4.5 GHz band has been realized. The results showed that the tapered drain line approach increased the power-added- efficiency from about 11% to 24% across the 4.5 GHz band. This relatively high value of efficiency for a DA is comparable to the 27% power-added-efficiency of the reactively matched power amplifier. Acknowledgment The authors would like to thank Mr. Balamurugan Sundaram and Mr. Sureshbabu Sundaram, graduate students, Department of Electrical and Computer Engineering, Bradley University, for preparing the illustrations and formatting this paper. http://cegt201.bradley.edu/rfpage Transistor: NE 721 ; Number of transistors: 4 Amplifier DC-Bias: V ds = 3V; V gs = -0.74V; I ds (total) = 120 mA Circuit Boards: Gate line : ε r = 3.1; h = 30 mil Drain line: ε r = 10 ; h = 25 mil Heat Sink material: Brass A four-stage balanced power amplifier. Conventional Distributed amplifier Measured third and fifth order intermodulation levels versus input power.