1. Microwave Amplifier Design Blog by Ben (Uram) Han and Nemuel Magno Group 14 ENEL 434 – Electronics 2 Assignment 2012 1

2. Specifications Bandwidth is defined as the narrower of the gain or input and output reflection coefficient bandwidths, where the gain bandwidth is determined by the 1dB points in the gain response, and the reflection coefficient bandwidth I where it is less than -10dB. 2 Centre frequency1075 MHz Bandwidth5 – 20% TransistorBFR92A GainComparable to maximum available gain Supply voltage12V Generator and load impedances50 + j0 Ω Input and output connectorsBNC and RG58 cable PCB1.6mm FR4 (Measured ε r =4.38) SMT package1206 resistors and 0805 capacitors Maximum board size140 mm x 100 mm

3. Microstrip Calculations We want to match the characteristic impedance of the microstrip to the connecting cables, i.e. 50Ω. We are given the measured dielectric constant (4.38), the PCB height (1.6mm), and the microstrip material and thickness (copper, 0.038mm). Using Txline to calculate the width of microstrip required we get: For a 50Ω copper track, the width is 3.025mm. The wavelength is 153.3mm. 3

4. Emitter Degeneration 1 In order to improve the stability of the amplifier at low RF frequencies a resistance will be placed between the emitter and the ground, providing negative feedback and stopping oscillation. At our center frequency however we want to reduce emitter degeneration to improve gain. The emitter bypass capacitor will be connected in parallel to the emitter resistor and should provide a low impedance path to ground for the RF signal at the target frequency. 4 Ideally we would set the series resonance frequency of the capacitor to match our center frequency. At 1075MHz the capacitor datasheet indicates that the capacitance should be ~20pF. This seems quite small compared to the collector capacitance of the transistor (~1pF). We will try a 100pF capacitor as an emitter bypass.

5. Emitter Degeneration 2 5

6. Bias Calculations 1 6

7. Bias Calculations 2 7 Pick from the E24 range, say 150Ω, then R 1 = 5R 2 = 750Ω. Simulation using R E = 100Ω, C E =100pF, R 1 = 750Ω, R 2 = 150Ω, R C = 360Ω, results in the following bias condition: Which shows that the assumption V be = 0.7V was slightly low, hence I C is also slightly lower. Tweaking the value of R 2 to 160Ω gives the better result below, so we will use that instead.

8. Active 2-port Schematic The schematic below shows the transistor and emitter degeneration (plus the DC biasing) which was simulated to obtain the S-parameters. The section inside the box will not be changed throughout the rest of the design. 8

9. Active 2-port Circuit Layout Below is a layout diagram showing the physical layout of the active 2-port section of the circuit (without the DC bias components, they will be included later). 9

10. Active Device K-factor and Maximum Gain Since we have |S 11 | 1 for unconditional stability. We can see from the graph below that the amplifier is unconditionally stable above 369MHz. The maximum gain available at the target frequency is 9.907dB. 10

11. S-parameters 1 From simulation of active 2-port in MWO, we get the following graphs. We will use these S-parameter values in our design calculations. 11

12. S-parameters 2 Using Microwave Office to simulate the DC bias conditions, the S parameters of the active two-port amplifier are read from the output graphs and are listed below: Using the equations given in Pozar Ch.12, the required values for Г S and Г L to achieve simultaneous conjugate matching are: Г S = 0.1081/174.2 °Г L = 0.6696/22.63° (Calculations and working are shown on the next slide) So we need to design matching networks using Smith charts to convert the 50Ω generator and load, to Г S and Г L respectively. 12 S 11 = 0.3588 / -15.59°S 12 = 0.1645 / 72.2° S 21 = 2.422 / 73.7°S 22 = 0.6298 / -21.56°

13. Simultaneous Conjugate Matching Calculations 13 The quadratic from conjugate matching provides two solutions. We want the reflection coefficient with an absolute value of less than 1. The other solution lies outside the Smith chart and indicates a negative resistance.

14. Matching Network (load end) 14 b=-1.8 S/C

15. Matching Network (source end) 15 b=-0.23

16. 16 ГSГS ГLГL The simulation results confirm matching networks provide the expected reflection coefficients small errors (due to graphical errors when using Smith charts) Simulation of matching networks made up with ideal transmission lines. Port 2 is used to provide a 50Ω termination in place of the generator or the load.

17. 17 ГSГS ГLГL Г1Г1 Г2Г2 Checking the design calculation for the simultaneous conjugate matching. The value for Г 1 is slightly out. We will try to correct this with fine tuning when the matching networks are implemented with microstrips.

18. 18 Completing the circuit using the ideal transmission line matching networks gives the results shown in the graph below. The gain is acceptable at our center frequency and the reflection coefficients are at their minimum. This shows our calculations were valid.

19. 19 Amplifier Test using Microstriplines 1 Ideal transmission lines are replaced with microstrips and Port-2 provides the 50 ohm termination ГSГS

20. 20 Amplifier Test using Microstriplines 2 ГLГL Ideal transmission lines are replaced with microstrips and Port-2 provides the 50 ohm termination

21. 21 Amplifier Test after Fine Tuning – Input In this section a T-junction discontinuity model has been added. The amplifier has also been fine-tuned so that Г S reflects the desired calculated value more closely (at least in simulations). Ideally: Г S = 0.1081/174.2 ° After Fine Tuning

22. 22 Again fine-tuning has been used to adjust the lengths of microstrip to achieve a closer match to the calculated value of desired Г L. Ideally: Г L = 0.6696/22.63° Amplifier Test after Fine Tuning – Output

23. 23 Matching Network and Layout 1 ГSГS ГSГS ГLГL ГLГL These are the layouts associated with each matching network.

24. Amplifier characteristics with microstrip matching networks and ideal bias feeding network 24 The bandwidth is limited by the -10dB point of the output reflection coefficient on the lower bound and the -1dB gain point on the upper bound. This gives a BW of 16.3%

25. RF Short Circuit Stub Termination 1 25 The value for the capacitor used to short the RF signal to ground at the end of the stub needs to be chosen to be resonant with its parasitic inductance to ensure a good connection to ground. However the impedance is significant for lower frequencies which may cause the signal to leak into the bias circuit. To resolve this situation we will add a second larger capacitor in parallel.

26. 26 RF Short Circuit Stub Termination 2 The resistor is necessary to avoid parallel resonance between the two capacitors. The setup shown has better characteristics across the frequency range of interest.

27. Complete Amplifier Design - Schematic 27 The final design schematic with DC bias network implemented with microstrips and all other components included.

28. Input Matching Network – Schematic 28 To base To bias network

29. Output Matching Network – Schematic 29 To collector To bias network

30. DC Bias Network 1 - Schematic 30 This is the lower left section of the complete design showing the resistor divider for the base terminal bias and the bulk capacitor for the power supply decoupling.

31. DC Bias Network 2 - Schematic 31 This is the lower right section of the complete design showing the collector resistor and further decoupling for the power supply.

32. Complete Amplifier Design Response 32 This graph shows that the final design has a healthy response at the desired center frequency and a BW of 15.3% which matches the specification. Simulating with a very large 1H inductance on each of the supply lines shown insignificant variation in the response.

33. Graph of Current vs Frequency 33 There is some leakage current going into the power supply, EMI filtering could be used if needed.

34. Complete Amplifier Design - Layout 34

35. PCB Layout mask 35 The PCB layout ready for fabrication.