18 July 2001 Work In Progress – Not for Publication 2001 ITRS Test Chapter ITRS Test ITWG Mike Rodgers Don Edenfeld

18 July 2001 Work In Progress – Not for Publication ITWG Membership New for 2001 New members from ATE, DFT EDA and expanded Semiconductor Manufacturers

18 July 2001 Work In Progress – Not for Publication For Component Test, the Constant is Change At-speed functional test Wide / slow interface buses Single technology designs Constant cost of test Capital Re-use Defect based test methods Narrow / fast interface links Multiple technology designs Declining cost of test New DFT and Test Methods

18 July 2001 Work In Progress – Not for Publication Key Challenges High speed device interfaces –Test instruments for characterization –Device interface capabilities (probes, sockets, etc) Highly integrated designs & SOCs –Low cost, highly configurable equipment platforms –DFT to simplify manufacturing test methods Reliability Screens running out of gas –Burn-in vs thermal runaway, Iddq vs dramatic leakage increase –Fabless industry growth increases the risks Reducing Manufacturing Test Cost –Capital equipment re-use across nodes –Increasing differentiation Manufacturing vs Verification ATE –Wafer level test, parallel test, wafer level Burn-in Test software standards –Increase productivity and decrease time to market –Improve equipment, EDA, test generation tools interoperability Modeling and simulation –Pre-silicon Simulation of the electrical test environment, test content –Seamlessly integrated to design CAD tools, environment

18 July 2001 Work In Progress – Not for Publication At-speed Functional Test Declines Use of at-speed functional test for products in the performance segment continues to decline for manufacturing –Driven by test development time and manufacturing cost pressures –Product development will continue to require at-speed functional test –The performance segment has traditionally driven the test equipment envelope –At-speed functional test will continue to be used in device characterization and manufacturing for lower performance devices –Increasing differentiation of manufacturing & verification ATE and methods

18 July 2001 Work In Progress – Not for Publication Demand for Bandwidth Penetration of high speed interfaces into new designs is increasing dramatically –Across product types & market segments –Demand for bandwidth pushes data rate –Demand for scalability and portability drive narrower data paths –Narrow data paths allow more device interfaces within a reasonable package pin count –More device interfaces drive an increase in the number of high speed interfaces per device –No clear cost effective equipment solutions exist for leading edge data rates and/or devices with many ports –DFT & test methods to enable lower than end use speed test

18 July 2001 Work In Progress – Not for Publication High Integration Devices & SOC Increasing integration will drive test complexity over the foreseeable future –Combination of different classes of circuits single die from separate unique DFT & manufacturing test legacies –BIST & DFT for mixed signal & RF applications is relatively immature and not industrial strength –The industry must identify methodologies and equipment to test such designs cost effectively e.g. IEEE P1500

18 July 2001 Work In Progress – Not for Publication Reliability Screens Run Out of Gas Burn-in –Thermal runaway Voltage Stress –Lowered application Vdd reduces Vdd-stress Iddq –Normal leakage currents dramatically increasing New materials –Rate of introduction increasing: Cu, low k, high k, SiGe –Increasing mechanical sensitivities –New packaging, assembly processes Rapid growth of Fabless business model –Organizational and corporate boundaries –Lack of clear ownership of reliability in distributed business models Critical need for new techniques for latent defects

18 July 2001 Work In Progress – Not for Publication Scaling Component Test Cost Test capital re-use across technology nodes –Driving more DFT and new test methods –Manufacturing Test ATE differentiated from Verification ATE –Manufacturing test at lower than application speed Highly parallel test –Multi-site or parallel test extending to logic and SOCs –Extending on memories from x32 and x64 to x128 –Increasing use of concurrent testing Wafer level probe Wafer level Burn-in Test during Burn-in –Increasing in memories –Extending to logic products

18 July 2001 Work In Progress – Not for Publication Momentum Builds for DFT Design For Test methods move test complexity on-chip and away from test equipment –Reduction in external I/O data rate, timing complexity, and/or channel count –Limit equipment capability growth to enable longer use and re-use cycles for leading edge products across nodes –Improve throughput by increasing parallel test opportunities –Over the next five years DFT insertion methods will continue to more effectively integrated into design processes driven by human resource needs and faster product cycles –Analog DFT will mature: formalization of analog techniques, simplification of analog manufacturing test

18 July 2001 Work In Progress – Not for Publication Test Software Standards Focus Standards for test equipment interface & communication are needed to decrease equipment integration time –Improve equipment interoperability to reduce factory systems integration time –e.g, built into 300mm equipment specifications Future: Needed standards for ATE software, test program generation to decrease test development effort and improve time to market –Increased focus for standards development and adoption of existing standards

18 July 2001 Work In Progress – Not for Publication Modeling and Simulation Electrical modeling is a necessity for high performance power and signal delivery –Complete modeling and simulation of the test environment will be a requirement –Including the test instrument, delivery path, and probe / socket parasitics Software simulation of test content against design models will provide dramatic improvement in time to market –Simulation of test environment must be improved to enable complete pre-silicon evaluation of test content –Seamless integration to rest of design EDA tools, environment

18 July 2001 Work In Progress – Not for Publication Key Challenges High speed device interfaces –Test instruments for characterization –Device interface capabilities (probes, sockets, etc) Highly integrated designs & SOCs –Low cost, highly configurable equipment platforms –DFT to simplify manufacturing test methods Reliability Screens running out of gas –Burn-in vs thermal runaway, Iddq vs dramatic leakage increase –Fabless industry growth increases the risks Reducing Manufacturing Test Cost –Capital equipment re-use across nodes –Increasing differentiation Manufacturing vs Verification ATE –Wafer level test, parallel test, wafer level Burn-in Test software standards –Increase productivity and decrease time to market –Improve equipment, EDA, test generation tools interoperability Modeling and simulation –Pre-silicon Simulation of the electrical test environment, test content –Seamlessly integrated to design CAD tools, environment