1. Key Trends High frequency serial interface data rate is scaling significantly faster than tester capability to test them High frequency (analog and digital) signal delivery and high performance power delivery to the DUT require new methodologies for tester interface board design The basic building blocks for an industry wide DFT tester equipment solution can and have been identified

2. Key Trends Wafer sales trends are increasing based on increasing trends towards multi-die packages, stacking, etc. Can the cumulative yield affect off all die in the package be avoided? Is KGD feasible? Embedded memory densities will grow to the point where dedicated memory tester insertions will be required during test - there has to be a better way… Test approaches and trends are increasingly driven by product market segment

3. Areas for Debate Application of advanced fault models is an area of controversy – must work with Design Need consistent roadmap trends for device pin count and I/O frequency – where should this come from? Design?