2. Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation

3. Presenters:Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation janusz_rajski@mentor.com Co-author: Jerzy TyszerPoznan Univ. of Technology Presenters:Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation janusz_rajski@mentor.com Co-author: Jerzy TyszerPoznan Univ. of Technology Presenters and authors

4. Tutorial ground rules  Definition: Embedded Test refers to design-for- testability techniques where testing is accomplished entirely or partially through on-chip hardware.  Disclaimer: This tutorial is not intended to endorse or discredit any commercial technology or product.

5. Audience   Designers of complex integrated circuits   IP core providers and integrators   Test engineers   EDA tools developers   EDA tools users   Researchers   Project managers   Designers of complex integrated circuits   IP core providers and integrators   Test engineers   EDA tools developers   EDA tools users   Researchers   Project managers Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test In particular: Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test In particular:

6. Tutorial objectives To present:  Compelling reasons for ET adoption  Common barriers for ET adoption  State-of-the-art ET fundamentals and practice  Architectures for logic and memory BIST  Embedded deterministic techniques  At-speed ET multiple-clock domain designs multi-frequency designs  Tools for BIST synthesis automation  Application examples and case studies

7. Outline  Introduction  Embedded stimuli generators  Compactors of test responses  Logic BIST  Deterministic forms of embedded test  Embedded at-speed test  Comparison of scan/ATPG, logic BIST and embedded forms of deterministic test  BIST schemes for embedded memory arrays  Summary of embedded test

9. Design characteristics CPU core MemoryASICASIC ASIC PLL IP core DSP core Memory IP core Memory Memory Memory ASIC Analog I / 0

10. System on Chip characteristics CPU core Memory ASIC ASIC ASIC PLL IP core DSP core Memory IP core Memor y Memory Memory ASIC Analog I / 0  System architecture  Microprocessors, DSP cores  Buses, peripherals, memory  ASIC portion  Structures: Logic, memory, analog  Multiple embedded memories: DRAM, Flash, CAM  Analog and mixed signal: PLLs, clock recovery  Field programmable logic  RF cores: wireless receivers  IP cores and reusable blocks available from multiple vendors  Design efficiency achieved by hierarchical core-based design style

11. New defects  Geometries shrink at 30% every three years  Defect sizes do not shrink in proportion  Increase of wiring levels from 6 to 9  Interconnect delays dominate  Gate delays reduced  Bridging faults

12. [Sematech, 1998] Sematech S-121 “Test Method Evaluation –Key Findings & Conclusions” Objective:  Evaluate various test methodologies Large sample size Extensive data collection & analysis

13. Sematech S-121  Device 116K equivalent gates  0.45 µm L effective (0.8 µm drawn)  50 MHz operating speed  249 signal I/Os  3 metal levels  Full LSSD Scan plus JTAG boundary scan 8 Chains, 5,280 master/slave LSSD latches (10,560 total latches)  Sample size 20,000 units  Test methods: Stuck-at faults, Functional tests, Transition delay faults & IDDQ

14. Sematech S-121 SAF - 99.5% coverage (8300 patterns) FUNC - 52% SAF coverage (532K cycles) IDDQ - >96% pseudo SAF coverage (195 patterns) Delay - 90% Transition coverage (15232 patterns) IDDQ 1463 FUNC 6 7 8 1 1251 13 SAF 6 0 52 Delay 14 34 36 FUNC IDDQ 1   Package test results (pre Burn-in)

15. S-121 Conclusions  All test methods detected unique defects  Near 100% SAF coverage missed many defects  Large defect coverage overlap between SAF & Delay SAF are a subset of Transition faults  IDDQ threshold setting significantly affects yield 98% of the IDDQ fails survived burn-in  Many (bridging) defects detected only by IDDQ But diminishing IDDQ effectiveness in DSM  Some Functional tests are still required  Opportunity to optimize test coverage levels & capital

16. BridgeM1-2 Bridge M2 Bridge M4 Break trans Bridge Poly M2 Bridge M3 Bridge M1-3 Bridge poly M1 Bridge M3-4 Open Poly Open Contact Bridge M1 Unknown Br Break M3 Bridge Poly M2 Break M2 Bridge M3-4 Break M1 Bridge Poly M4 Bridge Poly Unknown Via break Defect Pareto 350 nm Al 4-5 Levels Oxide Dielectric W Plugs 350 nm Process 5 million Transistors A Transistor Process Shrinks vs. Defect Types

17.  Defect distribution change with process 100 nm Process -- 250 million transistors A Transistor Cu (8 Levels) Low-K Dielectric Cu Plugs Unknown Defect Pareto 100 nm ? Process Shrinks vs. Defect Types

18. Defects vs. Fault Coverage [M. Rodgers, et. al. DAC 2000] 1101001000K-Ohms.18 um.25 um Test chip FA results Increasing defect populations causing more V DD, Temp, & freq sensitive device fails Bridge Defect Observed Resistance  Wired “AND” & “OR” models are not sufficient  Speed limiting defects  Frequency of bridging defects is increasing  Need to drive ATE & modeling requirements from the defects to be detected  Will drive need for more scan vectors

19. Quality requirements Y 1 - Y p 1 - p shipment Faultsdetected Escapes

20. Quality requirements p Yield = 0.1 Yield = 0.9 Escapes = (1 - Y)(1 - p)

21. Fault models  Stuck-at-0 and stuck-at-1   Transitions   Path delay   Multiple detects VDD

22. Very high test quality  Very high fault coverage  Wide range of fault models stuck-at transition path delay at-speed testing multiple detects bridging defect based cross-talk effects... fading IDDQ Coverage Escapes

23. High-performance MPU/ASIC gate count ITRS Roadmap 2001 Gate count

24. Scan chains  The pattern count for transition faults may reach 20,000

25. Scan test ATE Scan input channels Primary outputs Scan output channels Primary inputs

26. ATE cost Tester cost = b +  m p b - base cost (zero pins) m - incremental cost per pin p - number of pins High performance ASIC / MPU DFT tester Low performance Microcontroller 250 - 400 100 - 350 200 - 350 2700 - 6000 150 - 650 1200 - 2500 512 512 - 2500 256 - 1024 b [ K$ ] m [ $ ] p Test cost can be $0.05/second

27. Volume of scan test data Test cycles =  Patterns Scan cells Scan chains...

28. Scan test time Test time = Scan cells Scan chains... FrequencyPatterns

29. Scan test cost Shift frequency 20 MHz Gate count 10M Scan chains 32 Padding ratio 1.4 Scan patterns 20K Vector memory 64MV Reload penalty 2s Insertions4 Tester rate 0.05$ Scan cells 500,000 Cells per scan 15,625 Longest scan chain 21,875 Cycles437.5M Scan test time 21.9s Passes6 Reload time 12.0s Time pre device 87.5s Cost per device 4.4$ More

30. High-performance MPU/ASIC 32 channels 20,000 patterns Required ATE memory Gigabits/channel

31. High-performance MPU/ASIC 100 MHz scan shift Scan test time seconds

32. ATE accuracy vs. device speed  Tester accuracy will improve from 200 ps to 175 ps by 2012  Clock period will decrease to 330 ps  Margin of error for ATE approaches 50% clock period Device period ATE accuracy Accuracyrequired

33. Requirements for Embedded Test  Increasing device complexity, operating speed, and new fault models stress conventional scan based test: Exploding volume of test data Exploding volume of test data Increasing scan test time, and Increasing scan test time, and Escalating scan test cost Escalating scan test cost  Embedded Test is required to: Generate most of the test data on-chip Generate most of the test data on-chip Compacting test responses on-chip, and Compacting test responses on-chip, and Providing on-chip control for at-speed test Providing on-chip control for at-speed test

34. Very low cost  Dramatically reduced volume of test data (10-100X)  Dramatically reduced scan test time (10-400X) ATE Memory [Mvectors] 10X 10X Scan test time[s] 2M gates Scan/ATPG 16 scan chains 5k vectors 2s handler/index time 1 test 10MHz scan shift

35. Long term scalability 100X increase in 10 years! Volume in conventional DFT years

36. Radical compression is required!  Immediate 5-10X compression  Compression ahead of volume for 10 years Volume in conventional DFT Compression factor years

37. Radical compression is required Compression should be ahead of Moore’s law for 10 years! Volume in conventional DFT Compression factor Compressed volume years